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Visitor pr242
Visitor
2,086 Views
Registered: ‎07-22-2014

Artix 7 / Zynq LVDS input common mode voltage

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Hi,

 

According to the datasheet, VICM max is 1.424v. Is this really correct?

 

It seems very low and doesn't give much headroom since the output common mode is 1.2v and can be be as high as 1.424 which gives *zero* headroom.

 

On the Spartan 6 VICM is 2.35v.

 

Is this a typo in the Series 7 datasheets? I hope so. I can't believe it should be so low.... and LVDS_33 is no longer supported... Seems like a backwards step.

 

:-(

 

Cheers

Paul

 

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Xilinx Employee
Xilinx Employee
2,666 Views
Registered: ‎07-31-2012

Re: Artix 7 / Zynq LVDS input common mode voltage

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Hi,

 

This is not a typo and these are the correct tested specs. Even the V-6 datasheet ds152 shows it the same. 

 

If the termination is properly done at the receiver as discussed in Pg 90 of this link - http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf, then you should be fine. however to accommodate for your board characteristics, you should do IO simulations to get a better idea.

 

 

Thanks,
Anirudh

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Xilinx Employee
Xilinx Employee
2,667 Views
Registered: ‎07-31-2012

Re: Artix 7 / Zynq LVDS input common mode voltage

Jump to solution

Hi,

 

This is not a typo and these are the correct tested specs. Even the V-6 datasheet ds152 shows it the same. 

 

If the termination is properly done at the receiver as discussed in Pg 90 of this link - http://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf, then you should be fine. however to accommodate for your board characteristics, you should do IO simulations to get a better idea.

 

 

Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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