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Visitor panneerraja
Visitor
788 Views
Registered: ‎11-07-2016

Artix7 PLL with wide input frequency range

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Dear Sir/Madam, 

I am using a custom board with no external Oscillator, so therefore i have to rely on CFGMCLK clock from Startup primitive.

Our Microblaze processor system contains block ram to store the program code. we have observed,on power-on, micro blaze processor tries to fetch some instruction or tries to access
the Block Ram that contains the program code during the Startup time(the time Startup primitive EOS signal stays low), even though the active-high reset to the micro blaze processor
system is asserted. We have observed that Microblaze and its peripherals are driven by the CFGMCLK even when EOS signal stays low(Startup time) but asserted reset is not effecting anything on the processor system.
As a result,occasionally, program code stored in the block ram gets corrupted and Microblaze starts to behave differently. This is really a strange problem.

To work around this problem, CFGMCLK clock going into the Microblaze processor system should be stopped during the startup period.
Since the PLL adds initial delay of few microseconds to its output clocks, PLL shall be used whose clock output will drive the Microblaze processor system. As a result, Microblaze processor system will not see any clocks during the startup time.
Input and output clock frequency are set to 100MHz in the PLL.
Since the CFGMCLK clock frequency can vary between 30 MhZ and 90 MHZ, will the PLL be able to handle the wide range of input clock frequency and keep the Multiply/Divide ratio as 1?

Kind Regards

Panneer-Raja Vajravelu.

1 Solution

Accepted Solutions
737 Views
Registered: ‎01-22-2015

Re: Artix7 PLL with wide input frequency range

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Panneer-Raja Vajravelu,

UG472 warns us numerous times about keeping fVCO within the frequency min/max specifications.  However, I cannot find mention in UG472 (or PG065) what happens when fVCO goes out of range.  Although your test results are most interesting ( thanks for sharing them ! ), I can only guess that PLL-lock and perhaps other features of the PLL are not guaranteed over Process-Voltage-Temperature (PVT) when fVCO limits are exceeded.

Mark

12 Replies
765 Views
Registered: ‎01-22-2015

Re: Artix7 PLL with wide input frequency range

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@panneerraja 

Since the CFGMCLK clock frequency can vary between 30 MhZ and 90 MHZ, will the PLL be able to handle the wide range of input clock frequency and keep the Multiply/Divide ratio as 1?

The procedure by which the PLL or MMCM creates an output clock from an input clock is described on about pages 72 and 76 of UG472.  This procedure involves parameters, M=CLKFBOUT_MULT_F,  D=DIVCLK_DIVIDE, O=CLKOUT_DIVIDE and the frequency, fVCO, of a VCO found inside the PLL/MMCM.  As described in Table 38 of DS181, fVCO has a frequency range from 800MHz to at least 1600MHz for the Artix-7 PLL.  The problem with the widely varying input, CFGMCLK, to the PLL is that fVCO may go out of range.  You can investigate this using the Clocking Wizard as I described in <this> post.

Cheers,
Mark

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Visitor panneerraja
Visitor
750 Views
Registered: ‎11-07-2016

Re: Artix7 PLL with wide input frequency range

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Dear Mark,

Thanks a lot for the reply. After investigating it using the Clocking Wizard, It looks like fVCO is going out of range for any input clock frequency below 80MHz. 

A test has been made under the following setup,

1) external clock generator generates clocks ranging from 10 MHz to 100MHz and driving it to the Artix7 PLL where input and output clock are set to 100MHz.

2) Input and output clocks of the PLL are monitored in the Oscilloscope.

Test result:-

there are corresponding output clocks generated for all input clock frequencies ranging from 10MHz to 100MHz. that is, if 30MHz is fed, 30Mhz output clock gets generated.

it seems like PLL/MMCM seems to generate the output clock even when fVCO goes out of working range. For ex., fVCO is just 100 MHz(which is far away from the specified range of 800MHz and 1600MHz) for the 10 MHz input clock frequency.

Please advise.

 

Kind Regards

 

Panneer-Raja Vajravelu

 

 

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738 Views
Registered: ‎01-22-2015

Re: Artix7 PLL with wide input frequency range

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Panneer-Raja Vajravelu,

UG472 warns us numerous times about keeping fVCO within the frequency min/max specifications.  However, I cannot find mention in UG472 (or PG065) what happens when fVCO goes out of range.  Although your test results are most interesting ( thanks for sharing them ! ), I can only guess that PLL-lock and perhaps other features of the PLL are not guaranteed over Process-Voltage-Temperature (PVT) when fVCO limits are exceeded.

Mark

Visitor panneerraja
Visitor
678 Views
Registered: ‎11-07-2016

Re: Artix7 PLL with wide input frequency range

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Hi Mark,

thanks again for the reply.

I was actually running the PLL in the Jitter Filter mode where input frequency gets regenerated on the output(Fout = Fin). Does out of range fVCO really matter when the PLL works purely as a Jitter Filter and not as a Frequency Synthesiser?

Page nr. 72 in UG472 says that Fout  is only the function of FClkin * (M/(D*O)). if this is true(seems true from the test results), why is  fVCO not affecting the Fout?

P.S. I also made the similar test on the PLL configured as frequency synthesiser with same Input and output clock frequency settings. PLL seems to work well for all input frequencies ranging from 10 to 100 MHz.

Kind regards

Panneer-Raja Vajravelu.

 

 

 

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660 Views
Registered: ‎01-22-2015

Re: Artix7 PLL with wide input frequency range

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Paeneer-Raja,

Very good questions!  Also, your interesting test results seem unexpected.  I will ask friends about this and try to get some answers for you.

Meanwhile, you might think about routing CFGMCLK through a BUFGCE instead of an MMCM.  Perhaps you can use EOS signal coming from STARTUPE2 primitive (UG953, pg595) to control CE pin on BUFGCE - and thus delay sending of CFGMCLK to your Microblaze processor system.

Mark

 
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Scholar markcurry
Scholar
636 Views
Registered: ‎09-16-2009

Re: Artix7 PLL with wide input frequency range

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(Preliminaries: I am not a PLL designer)

The basics of PLL operation (glossing over a lot of details) basically generate an  FClkout= FClkin * (M/(D*O)) - whether in "Frequency Sythesis mode" or "Jitter reduction mode".  In basic terms for the latter mode the ratio (M/(D*O)) = 1.

There are many qualifications that must be met in order for the PLL to operate within spec - these can include min and max frequencies of the phase detector, as well as the VCO.  Operating a device outside the supported rangee and the device is no longer guaranteed to generate an output to spec.

The basics of the PLL (configuration) don't change by changing the input reference clock frequency - it's still going to (try) and track the input clock.  Noise performance, locking characteristics and other parameters are just no longer guaranteed. 

I'd strongly suggest - keeping the PLLs (in any circuit, from any vendor) to be within vendor spec.  PLL failures can manifest in very odd, unpredictable ways.

Regards,

Mark

Historian
Historian
627 Views
Registered: ‎01-23-2009

Re: Artix7 PLL with wide input frequency range

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As @markcurry  said, there isn't a separate "jitter reduction" mode or "frequency synthesis mode" - the operation of the PLL is always the same.

The VCO runs at a frequency of fIN*M/D.

The outputs run at a frequency of fVCO/O.

In your case, you want your fIN to be fOUT, so that just means that O=M/D.

The specifications state (pretty clearly) that fVCO must remain within the legal range. When you lower the fIN, then the fVCO also changes, and quickly leaves the valid range for fVCO. But your observations are that the system "appears" to still work, even though your are violating the fVCO mimimum limit.

It is important to note that the PLL is an analog device. Like all Silicon based circuits, the performance of the transistors are highly process/voltage/temperature (PVT) dependent. When a device parameter is specified in a datasheet, it is guaranteed over the whole allowed range of PVT. In the case of fVCO, this means that the PLL is guaranteed to operate at all PVT corners only if fVCO remains in the specified legal range. If you are outside this range it may work at some PVT corners, but it is not guaranteed to do so over the entire PVT range.

Furthermore, even if it nominally "works", it may not be operating properly. For example it is possible that when operating outside the legal range:

  • The output jitter may be higher than specified
  • The lock time may be longer than specified
  • The phase alignment may have more error
  • (or some other things)

The only thing we know is that if the fVCO (and other parameters) are in the legal range, then all parameters of all devices at all PVT corners will be within the ranges specified in the datasheet. If we are not in the fVCO legal range, then none of these are guaranteed.

Avrum

Visitor panneerraja
Visitor
601 Views
Registered: ‎11-07-2016

Re: Artix7 PLL with wide input frequency range

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Mark,

>>Meanwhile, you might think about routing CFGMCLK through a BUFGCE instead of an MMCM.  Perhaps you can use EOS signal coming from STARTUPE2 primitive >>(UG953, pg595) to control CE pin on BUFGCE - and thus delay sending of CFGMCLK to your Microblaze processor system.

I did exactly this in one of my trail run. but it's observed that there are about 20to25 clocks are buffered before BUFGCE takes the de-asserted control pin CE(EOS) into account and blocks the clocks till EOS assertion. I was able to see some transaction on the Instruction memory bus of Bram during the time EOS stays low.

the only logic that helped blocking the clock during startup time is as follows,

entity mimicPLL is

port (
 osc_clk  : in std_logic := '0';  --CFGMCLK
 eos_in  : in std_logic := '1';  -- Startup flag. 
 osc_clkO : out std_logic := '0'; -- Delayed cfgmclk
);
end entity;

architecture rtl of mimicPLL is
 
signal cnt8    : integer range 0 to 15 := 0;
signal eos_d,eos_dd  : std_logic := '1';
signal osc_clkOt  : std_logic := '1';
 
begin

process(osc_clk)
 begin
  if rising_edge(osc_clk) then
   eos_d <= eos_in;
   eos_dd <= eos_d;
  
   if eos_dd = '0' then   -- Hold Counter to zero when EOS
    cnt8 <= 0;
   elsif (cnt8 /= 15) then 
    cnt8 <= cnt8 + 1;   -- increment the Counter when EOS is high and stop counting at 15.   
   end if;
 
  end if;
 end process;
 
osc_clkO <= osc_clk when (cnt8 >= 7) else '1'; -- Hold CFGMCLK clock output to high when EOS is low. when it's high and counter reaches 7 or above, bypass it.
 
end rtl;

when observed in the Scope, there were no glitches found on the delayed output clock when EOS gets asserted.

The output clock is held high '1' during the Startup time(EOS low period), then first output clock transistion(falling edge) takes place when LUT switches from '1' to input clock. timing constraint was mentioed for this generated clock and there are no timing violation observed.

 

Raja.

 

 

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Visitor panneerraja
Visitor
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Registered: ‎11-07-2016

Re: Artix7 PLL with wide input frequency range

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Avrum,

Thanks for the reply.

Raja.
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Visitor panneerraja
Visitor
596 Views
Registered: ‎11-07-2016

Re: Artix7 PLL with wide input frequency range

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Mark,

Thanks for the reply.
Raja.
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572 Views
Registered: ‎01-22-2015

Re: Artix7 PLL with wide input frequency range

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Hi Raja,

Congratulations on getting things working - and thanks for sharing your solution code.

-a few comments about your code:

1)  Bring osc_clk in through a BUFG to officially put it in the FPGA clock tree.

2)  Set property, ASYNC_REG=TRUE, for the two registers in your synchronizer as follows.  This will ensure these two registers are placed physically close to each other and make the synchronizer work properly.

attribute ASYNC_REG : string;
attribute ASYNC_REG of eos_d, eos_dd: signal is "TRUE";

3) The following line is an unconventional way to send a clock out of the FPGA and is prone to glitching because it does not "register" osc_clkO.

osc_clkO <= osc_clk when (cnt8 >= 7) else '1';

Instead, consider using the ODDR circuitry shown in Fig. 2-18 of UG903 to send osc_clk out of the FPGA.  Your control/delay logic can control the CE pin on the ODDR to stop/start the forwarded clock.

Mark

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Visitor panneerraja
Visitor
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Registered: ‎11-07-2016

Re: Artix7 PLL with wide input frequency range

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Hi Mark,

Thanks for the reply.

1)  Bring osc_clk in through a BUFG to officially put it in the FPGA clock tree.

it's already done inside the wrapper module where  Startup primitive gets instantiated.

2) thanks for the idea.

3) 'osc_clkO' is internal-only clock to clock microblaze processor system. Using ODDR for internal purpose does not work.

 

Raja.

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