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Adventurer
Adventurer
5,245 Views
Registered: ‎11-22-2016

Aurora 8B/10B Example Design Issue

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Hello,

I am trying to simulate Aurora 8B/10B example design(Streaming interface, Duplex with a lane width 2), in Xilinx Vivado 2016.4. But once I click run behavioral simulation. I am getting the following error.

 

INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'E:/NOW/manoj/ESM_PROCESSOR/Aurora/ip_project/Aurora_IP/aurora_8b10b_0_ex/aurora_8b10b_0_ex.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "aurora_8b10b_0_TB_behav -key {Behavioral:sim_1:Functional:aurora_8b10b_0_TB} -tclbatch {aurora_8b10b_0_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2016.4
ERROR: unknown error occurred
ERROR: [USF-XSim-62] 'simulate' step failed with errors. Please check the Tcl console or log files for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:01:12 . Memory (MB): peak = 2103.840 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

Any help would be appreciated.

 

Thank you,

Manoj

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

Yes all the license should only have a limit for newer versions.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

I am able to reproduce your issue. I am investigating.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

This is an issue with the VHDL example design. If you generate it in verilog you will have no issue.

 

To generate it in Verilog, change your target language to Verilog before clicking on open example design.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
5,223 Views
Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Hi Florent, 

Thanks for getting back. I tried with Verilog option, and still the same error persists.

Do you think there is an issue with my tool itself?

 

Thanks,

Manoj

 

WARNING: [Common 17-306] Update version (2014.3_AR63362) does not match product version (2016.4).

****** Webtalk v2016.4_AR63362 (64-bit)
**** SW Build 1733598 on Wed Dec 14 22:35:39 MST 2016
**** IP Build 1731160 on Wed Dec 14 23:47:21 MST 2016
** Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.

source e:/NOW/manoj/ESM_PROCESSOR/Aurora/ip_project/Aurora_IP/example_verilog/aurora_8b10b_0_ex/aurora_8b10b_0_ex.sim/sim_1/behav/xsim.dir/aurora_8b10b_0_TB_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] 'e:/NOW/manoj/ESM_PROCESSOR/Aurora/ip_project/Aurora_IP/example_verilog/aurora_8b10b_0_ex/aurora_8b10b_0_ex.sim/sim_1/behav/xsim.dir/aurora_8b10b_0_TB_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Thu Mar 09 18:50:53 2017. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/Vivado/2016.4/doc/webtalk_introduction.html.
webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 50.570 ; gain = 0.512
INFO: [Common 17-206] Exiting Webtalk at Thu Mar 09 18:50:53 2017...
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:01:13 . Memory (MB): peak = 854.594 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '73' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'e:/NOW/manoj/ESM_PROCESSOR/Aurora/ip_project/Aurora_IP/example_verilog/aurora_8b10b_0_ex/aurora_8b10b_0_ex.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "aurora_8b10b_0_TB_behav -key {Behavioral:sim_1:Functional:aurora_8b10b_0_TB} -tclbatch {aurora_8b10b_0_TB.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2016.4
ERROR: unknown error occurred
ERROR: [USF-XSim-62] 'simulate' step failed with errors. Please check the Tcl console or log files for more information.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:01:19 . Memory (MB): peak = 854.594 ; gain = 0.000
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.

 

 

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Moderator
Moderator
5,221 Views
Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

To make it work in VHDL, open the VHDL file aurora_8b10b_0_support.vhd

1.JPG

 

And then comment l113 to l118

2.JPG

 

Then it should work.

 

I will tell development about this issue in the example design.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
5,218 Views
Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Florent,

It seems like a tool issue, as it is giving the same error for another design as well. Let  me explore on my end as well.

 

Note that we are using a Vivado 2016.4. 

 

 

 

Regards,

Manoj

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Moderator
Moderator
5,217 Views
Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

You are not suppose to have this warning:

Update version (2014.3_AR63362) does not match product version (2016.4).

 

Could you open the repport IP and see if the IP is up to date in your project?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
5,106 Views
Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Hi Florent, I checked the report IP status, and the IP seems to be fine. As you pointed out with the following warning, "You are not suppose to have this warning: Update version (2014.3_AR63362) does not match product version (2016.4)". The above warning seems to be the issue. Forget Aurora IP, I got the same warning for even a simple and gate simulation. I figured out there was an old patch file from 2014.3 which was pointed out in my environment variable as "My_Vivado". I deleted that particular environment variable, and also the 2014.3 patch from my system. Now when I try to simulate, I am getting the following error(Please see attachment). What do you think might be the issue Florent?. Thanks for your time, Manoj
simulation_error.PNG
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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Florent,

Note that the following warning is gone after I deleted the above mentioned patch file and environment variable.

 

You are not suppose to have this warning:

Update version (2014.3_AR63362) does not match product version (2016.4).

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Re: Aurora 8B/10B Example Design Issue

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Hello @manoj_xilinx,

 

Can share all the three log files i.e. compile.log , elaborate.log and simulate.log?

They should be present in sim folder of project directory.

Regards,
Ashish
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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Hello Ashish,

Sure, here we go.

 

Regards,

Manoj

 

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

Could you try to create a new project with 2016.4 (with target language Verilog first) > add and configure the IP > generate the example design and let us know if this is working.

 

If not could you attached both projects (main + example) to this thread.

 

Thanks,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Hello Florent,
Please see the attached zip folder which contains main project created in vivado 2016.4, with target language as verilog. The simulation still fails.

Note that in my case, the simulation fails and throws the same error even for a simple and gate or a flip flop design.

Simulation now throws the same error in all the cases.(See simulation_error.PNG attached).

Thank you,
Manoj

simulation_error.PNG
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Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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The example design exceeds 25MB when compressed, hence I couldn't post it  here.

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Re: Aurora 8B/10B Example Design Issue

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Hello @manoj_xilinx,

 

As you have mentioned that simulation fails even with simple gate or flip-flop design, Aurora example design can't be culprit here.

It looks me like some intermittent corruption issue. Few suggestions which can help -

 

1. Are you facing this problem from the time you installed the tool? Or was it working initially and then stopped invoking?

2. Can you check Tcl console (attach vivado.log file here) as mentioned in the error message, to see if it has some clue?

3. Can you try invoking the tool in 32-bit mode and let us know if you face the same issue? This AR will help you for the same -

     https://www.xilinx.com/support/answers/47821.html

4. Re-installation of the tool has helped in some of issues observed earlier. You can think of this option as last resort.

Regards,
Ashish
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Moderator
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Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

Oh ok. So if it is not related to the IP, this is an issue with the tool.

 

What I can suggest you:

1. Try to check in the simulation settings that you are targeting the vivado simulator

2. Check if Vivado 2016.4 in in you Environment Path:

1.JPG

 

2.JPG

3. If this is not working, try to reinstall vivado

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Hi Ashish,

1. I am facing the problem right from the time of installation.

2. The Tcl console doesn't give any clue. It simply says simulation failed.

3. I tried invoking in 32 bit mode. The issue is still there. Note that I am using 64 bit windows OS.

4. I have reinstalled the tool twice so far. I just reinstalled once today, after deleting the 2014.3 patch folder.

 

Thanks,

Manoj

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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Hello Florent,

1. The simulation settings seems to be fine. It is pointed to vivado simulator.

2. I tried setting the environment path as you mentioned to win64.o and bin.But no help.

3. Yes, reinstalled and checked too. Not working.

 

Do we need to play around with User variable ?.

 

Thanks,

Manoj

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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Hi Florent and Ashish,

Any other work around for me?.

 

Thanks,

Manoj

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

Did you tried on another machine to see if you had the same issue?

 

Could you check that you don't have any other version than 2016.4 in your environment path?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Re: Aurora 8B/10B Example Design Issue

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Florent,

1. Yes I tried in another machine, and it works fine. But, I need this to work in mine. 

2. How do you check this exactly?. Can you please brief this?.

 

Let me attach my environment path of my system.

Note that even after adding the couple of files to the path as you mentioned, it didn't work(win64.o and bin)

 

Thanks,

Manoj

Capture.PNG
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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Is there any way to check if any of my older installations of vivado(2014.3/2014.4) is being the culprit here?

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Moderator
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Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

If you open the environment variable PATH, check if there it includes path to Xilinx installation path.

 

Check if there is a XIlinx or Xilinxd environment variable


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Florent,

There is no xilinx installation path listed in Path(environment variable).

I don't see any Xilinx or Xilinxd environment variable.

 

The only thing which I see pertaining to xilinx is this.(See attached).

 

Please advice.

 

Thanks,

Manoj

System_Variable.PNG
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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Hello @florentw@ashishd

This problem is not yet solved, and hence I need to run simulation soon, I am planning to uninstall Xilinx Vivado 2016.4, and download a previous older version. Will I able to generate a trial license from the same computer if I install a older version?

 

Thanks,

Manoj

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

You should be able to use the same license if you use an older version of vivado.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
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Re: Aurora 8B/10B Example Design Issue

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Thanks Florent, I am planning to download Vivado 2014.4, so the existing 2016.4 licence should be fine for 2014.4?

 

Regards,

Manoj

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Xilinx Employee
Xilinx Employee
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Registered: ‎02-14-2014

Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

Yes it should work for 2014.4.

Regards,
Ashish
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Re: Aurora 8B/10B Example Design Issue

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Hi @manoj_xilinx,

 

Yes all the license should only have a limit for newer versions.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎11-22-2016

Re: Aurora 8B/10B Example Design Issue

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Thanks @florentw and @ashishd for helping out. Downloaded 2014.4, and used the same licence(2016.4's licence). Simulation works fine now.

 

Regards,

Manoj

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