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Observer johnpat163
Observer
7,477 Views
Registered: ‎09-01-2014

Burst-Mode Clock Data Recovery

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Good evening,

 

I am currently working on a project that requires burst clock data reocvery(BCDR), similar to the PONs.

We are currently using 7-series boards (VC707,VC7222) that as far as i know, do not suppport burst clock data recovery.

 

I found on XAPP152 (http://www.xilinx.com/support/documentation/application_notes/xapp1252-burst-clk-data-recovery.pdf)

that Xilinx's Ultrascale Devices can support BCDR by using the BCDR quick-lock circuit (link above).

 

I want to ask

1) why this core is available only for Ultrascale Devices and

2) is it possible to implement a similar circuit for the 7-series boards mentioned above?

 

Thanks in advance,

John

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1 Solution

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Scholar austin
Scholar
14,397 Views
Registered: ‎02-27-2008

Re: Burst-Mode Clock Data Recovery

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j,

 

1.  Ultrascale devices have new circuits designed just for these applications.

 

2.  Without those new features, there is no way to do the same in older products, but...

 

Over-sampling a data stream, and post processing does remain a method to recover bursty data.  So, depending on the data rate, running at a fixed higher rate all the time is a means to use in the older technologies.

 

Look at xapp592 (not exactly what you want, but may be useful).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
5 Replies
Scholar austin
Scholar
14,398 Views
Registered: ‎02-27-2008

Re: Burst-Mode Clock Data Recovery

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j,

 

1.  Ultrascale devices have new circuits designed just for these applications.

 

2.  Without those new features, there is no way to do the same in older products, but...

 

Over-sampling a data stream, and post processing does remain a method to recover bursty data.  So, depending on the data rate, running at a fixed higher rate all the time is a means to use in the older technologies.

 

Look at xapp592 (not exactly what you want, but may be useful).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor xuwei_xue
Visitor
2,305 Views
Registered: ‎03-21-2017

Re: Burst-Mode Clock Data Recovery

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Hi Austin,
Now I use the xapp152 to achieve the quick clock recovery, but it doesn't work, do you know the answers to these problems? many thanks.
a) How do i choose Threshold, WaitTime and stepSize inputs?
b) Regarding sop, I understand that i have to create a component that searches the incoming data (gt0_rxdata) and when it recognizes the preamble it asserts '1' in the sop input. Is that right?
c) In XAPP1252 i can see that RXCDR_CFG2 must be equal with PON's preamble (x"0546"). Why is this happening? Is there a problem to use a preamble different than PON's (different size and bits)? could I use another type of preamble? like x"5555".

Thanks in advance,
Xuwei
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Scholar austin
Scholar
2,301 Views
Registered: ‎02-27-2008

Re: Burst-Mode Clock Data Recovery

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x_x,

 

Depending on the application, and the requirements, different values are required.

 

Depending on the settings, a maximum lock time may be found.

 

Recognition of the preamble is required before anything may be recovered.  That takes some time to resolve.  Different preambles may be used, but the preamble must be chosen for its ability to be quickly recognized.  I would not choose my own.

 

xapp 152 is power estimation.

 

What xapp did you really mean to refer to?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Visitor xuwei_xue
Visitor
2,296 Views
Registered: ‎03-21-2017

Re: Burst-Mode Clock Data Recovery

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Hi Austin,
Thank you very much for your reply
xapp1252 https://www.xilinx.com/support/documentation/application_notes/xapp1252-burst-clk-data-recovery.pdf
For me the BCDR block like a black box, I don't know its working principle. do you know any other documents relevant with the BCDR block?
I really want to know what the principle of setting these four parameters (Threshold, WaitTime, stepSize and Sop) is.

Thank you in advance
Xuwei
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Scholar austin
Scholar
2,290 Views
Registered: ‎02-27-2008

Re: Burst-Mode Clock Data Recovery

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xap1083 has more details,

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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