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Registered: ‎04-06-2017

Can I use ISE to develop 7 series FPGA project?

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Can I use ISE to develop 7 series FPGA project? Is there any bug for ISE in doing this. Is vivado preferred? Why?

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Registered: ‎01-22-2015

Re: Can I use ISE to develop 7 series FPGA project?

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@greatmaverick

According to Table 2-1 in UG631, ISE supports some 7-Series devices.  However, as Xilinx recommends <here> you should choose Vivado for your 7-Series work.  

Other reasons to use Vivado instead of ISE...

  • ISE is an end-of-life product (no updates since October 2013). 
  • Windows Users:  the standard ISE runs under WIN7 (and not WIN10) – although a special version for use only with the Spartan-6 runs under WIN10
  • Vivado is now widely used, meaning more people on this Forum can help you with Vivado questions than with ISE question.
  • Vivado timing analysis is more accurate than ISE timing analysis.  Avrum has often said [1] [2] [3] that ISE cannot properly do hold time analysis for FPGA output interfaces.

-just say NO to ISE.

Cheers,
Mark

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356 Views
Registered: ‎01-22-2015

Re: Can I use ISE to develop 7 series FPGA project?

Jump to solution

@greatmaverick

According to Table 2-1 in UG631, ISE supports some 7-Series devices.  However, as Xilinx recommends <here> you should choose Vivado for your 7-Series work.  

Other reasons to use Vivado instead of ISE...

  • ISE is an end-of-life product (no updates since October 2013). 
  • Windows Users:  the standard ISE runs under WIN7 (and not WIN10) – although a special version for use only with the Spartan-6 runs under WIN10
  • Vivado is now widely used, meaning more people on this Forum can help you with Vivado questions than with ISE question.
  • Vivado timing analysis is more accurate than ISE timing analysis.  Avrum has often said [1] [2] [3] that ISE cannot properly do hold time analysis for FPGA output interfaces.

-just say NO to ISE.

Cheers,
Mark