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Newbie conanmcb1
Newbie
1,560 Views
Registered: ‎10-04-2018

Can an I/O Bank in Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

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Hello,

 

Can an I/O Bank in an Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

 

If the answer is yes and it can safely be powered by 3.3V, what will happen to the switch thresholds and does the I/O clamp at 2.5 or output VCCO 3.3V? 

 

Will it cause any damage to the device?

 

Thanks

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Moderator
Moderator
1,364 Views
Registered: ‎04-18-2011

Re: Can an I/O Bank in Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

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Hi @conanmcb1

 

The passage you quote is correct. 

An output programmed as LVCMOS25 and the bank VCCO is later powered at 3.3V will not drive high and stop at 2.5V. 

It will drive rail to rail as you have read. Also the drive setting you set in the tools won't be as advertised. I would expect that the 8mA drive setting for a LVCMOS25 will have stronger drive high when powered at 3.3V. 

Also I expect that the propagation via the OBUF won't be as advertised in the DS or the timing tools. 

 

 

On the input side you won't cause damage to the IO but it will be guess work where your VIH and VIL logic level really are. 

Also I am not sure you will get the advertised propagation through the buffer. 

 

I hope this clears it up for you. 

 

Keith  

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Voyager
Voyager
1,390 Views
Registered: ‎08-16-2018

Re: Can an I/O Bank in Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

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Newbie conanmcb1
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1,384 Views
Registered: ‎10-04-2018

Re: Can an I/O Bank in Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

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Thank you for your answer.

Is there an explicit matrix from xilinx with the cross compatibility of LVCMOS standard with bank voltages? DS181 and UG471 talk about mixing standards in banks but not mixing voltages.
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Newbie conanmcb1
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Registered: ‎10-04-2018

Re: Can an I/O Bank in Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

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I have seen in other posts that;
"LVCMOS outputs drive from rail to rail, i.e. from ground to Vcco, regardless of the selected I/O standard. Thus you must use the correct Vcco to actually achieve the desired standard, e.g. 2.5V for LVCMOS25 and 3.3V for LVCMOS33."

Which contradicts your answer, therefore leaving me still confused!

Thanks
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Moderator
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1,365 Views
Registered: ‎04-18-2011

Re: Can an I/O Bank in Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

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Hi @conanmcb1

 

The passage you quote is correct. 

An output programmed as LVCMOS25 and the bank VCCO is later powered at 3.3V will not drive high and stop at 2.5V. 

It will drive rail to rail as you have read. Also the drive setting you set in the tools won't be as advertised. I would expect that the 8mA drive setting for a LVCMOS25 will have stronger drive high when powered at 3.3V. 

Also I expect that the propagation via the OBUF won't be as advertised in the DS or the timing tools. 

 

 

On the input side you won't cause damage to the IO but it will be guess work where your VIH and VIL logic level really are. 

Also I am not sure you will get the advertised propagation through the buffer. 

 

I hope this clears it up for you. 

 

Keith  

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Newbie conanmcb1
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1,350 Views
Registered: ‎10-04-2018

Re: Can an I/O Bank in Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

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Hi Keith,

Thank you for clarifying this issue. Is this the same with the other LVCMOS standards i.e. LVCMOS18 and LVCMOS15 too?

If we reverse the question and set the bank voltage to 2.5 with a LVCMOS33 standard in the FPGA image, what effect will this have?

Is this also the same for a Spartan-6 device?

Thank you again

Conan

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: Can an I/O Bank in Artix-7 using LVCMOS25 bidrectional/differential be powered by 3.3V?

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For Outputs:

This will be the same for all LVCMOS outputs it doesnt matter if you power it higher or lower than expected. 

 

Programming them to be one voltage level and then powering them differently will have the effect of giving you a drive setting that is not what you expect. 

The drive setting is really just the tools enabling parallel driver legs in the output. So more parrallel legs = more drive strength. 

LVCMOS25 8mA drive will equate to x ammount of driver legs say. (x is just an illustration, I don't know how many or how few mosfet channel are used on any given setting)

If you go and change VCCO to 3.3V then you still have "x" driver legs turned on whereas if you programmed LVCMOS33 with its 8mA drive setting then you would normally have x-y driver legs enabled. 

the point I am making is you will have no real idea of what your drive capability is. 

On the one hand (lowering the VCCO below what you expect when configuring the IO) this means you could have a driver that can problems driving the load you have placed on it. On the other hand (programming at one level and then increasing the VCCO) you are likely to get Signal integrity issue like ringing if the drive strength is too strong.

Then there is a chance your IO timing can be affected if you are doing it statically. 

 

For inputs:

If you tell the tools that the input is LVCMOS33 then you power vcco@2.5V and give it a 2.5V signal then the only impact is that you won't know for sure the VIL and VIH logic levels and propagation through the input buffer is not going to be what you expect from the Datasheet and Timing report. 

However, if you tell the tools that the input is LVCMOS33 then you power vcco@2.5V and give it a 3.3V signal you are in trouble because We have a Vin spec in the data sheet that is referenced to VCCO so absolute max VIN is VCCO+0.55V so  here there is a risk to overstress the input with too high a voltage. 

Furthermore, an input above VCCO will end up turning on the ESD clamp in the IO.When this is on there is a limit to amount of current you are allow to sink into it. this is Given by Iin in the data sheet. 

 

The Spartan-6 question is slightly different. 

The same VCCO requirement applies to outputs and powering them to different levels will result in the same unsupported situation described above. 

LVCMOS inputs are different in Spartan-6. There is no VCCO requirements on them you can have a LVCMOS33 input in bank powered at any valid VCCO. 

The exception to this is LVCMOS25. To host it in a bank whose VCCO is not 2.5V, VCCAUX must be set to 2.5V.

 

you can see this in UG381 table 1-5

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