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Observer therealpaulie
Observer
6,337 Views
Registered: ‎11-18-2009

Cascade 2 x DCM. Input for the second one is CLKFX

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Hi,

 

I know (from documentation and also from some other threads here on forum) that I can cascade two DCM (Digital Clock Manager) for a Spartan 3E.

 

What I didn't find anywhere (CORE Generation doesn't allow it) is to cascade two DCM like this:

Input Clock -> CLKIN (DCM no. 1) / CLKFX (DCM no. 1) -> CLKIN (DCM no. 2) ??

 

Is this configuration possible?

 

I would like to achieve a 256/625. This could be possible if both DCM have 16/25. (16/25 * 16/25 = 256/625). So the output from the first DCM - CLKFX must be connected to the input of second.

 

I'm going to try it anyway to see if it works (synthesis and simulation). If it works, are there some things that I must take into account??

 

Thanks,

Paul

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1 Solution

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Scholar austin
Scholar
7,966 Views
Registered: ‎02-27-2008

Re: Cascade 2 x DCM. Input for the second one is CLKFX

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Paul,

 

The FX output has more jitter (that the other DCM outputs), as a result of the synthesis used by the DCM (DFS).  The next DCM synthesizer (DFS) may not lock, may lose lock, or may just behave in a weird fashion (with too much jitter on its input).  That said, some combinations have much less jittter than other (M and D), and it will work.  We do not guarantee this mode of cascading DCM (FX->CLKIN) in DFS mode, but feel free to play around.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
7 Replies
Scholar austin
Scholar
7,967 Views
Registered: ‎02-27-2008

Re: Cascade 2 x DCM. Input for the second one is CLKFX

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Paul,

 

The FX output has more jitter (that the other DCM outputs), as a result of the synthesis used by the DCM (DFS).  The next DCM synthesizer (DFS) may not lock, may lose lock, or may just behave in a weird fashion (with too much jitter on its input).  That said, some combinations have much less jittter than other (M and D), and it will work.  We do not guarantee this mode of cascading DCM (FX->CLKIN) in DFS mode, but feel free to play around.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Highlighted
Observer therealpaulie
Observer
6,322 Views
Registered: ‎11-18-2009

Re: Cascade 2 x DCM. Input for the second one is CLKFX

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Hi Austin,

 

Thanks for your hint.

I tested it and it looks ok. There is some jitter but it doesn't seem to be very high (I have to measure it with another oscilloscope. Mine is to slow).

 

You said "may just behave in a weird fashion (with too much jitter on its input) ". The "weird fashion"  is only jitter or something else? Some jitter is not a big problem for me. I have to generate 2.048MHz from 20MHz without any hardware (PCB) updates. The generated clock is going to be used for a asynchronous serial interface where jitter up to +/- 10% from clock period is tolerated.

 

Therefor, if using two DCM in this configuration has only one drawback -> the jitter (hopefully <+/-10%), then I can live with it. Anyhow, I cannot see any better solution (resources and performance) to generate the needed clock in Spartan 3E.

 

Do you think my requirements are met in this configuration?

 

Regards,

Paul

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Scholar austin
Scholar
6,314 Views
Registered: ‎02-27-2008

Re: Cascade 2 x DCM. Input for the second one is CLKFX

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Paul,

 

Since we don't support this use case, I can't say antyhing more.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Instructor
Instructor
6,290 Views
Registered: ‎08-14-2007

Re: Cascade 2 x DCM. Input for the second one is CLKFX

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@therealpaulie wrote:

Hi Austin,

 

Thanks for your hint.

I tested it and it looks ok. There is some jitter but it doesn't seem to be very high (I have to measure it with another oscilloscope. Mine is to slow).

 

You said "may just behave in a weird fashion (with too much jitter on its input) ". The "weird fashion"  is only jitter or something else? Some jitter is not a big problem for me. I have to generate 2.048MHz from 20MHz without any hardware (PCB) updates. The generated clock is going to be used for a asynchronous serial interface where jitter up to +/- 10% from clock period is tolerated.

 

Therefor, if using two DCM in this configuration has only one drawback -> the jitter (hopefully <+/-10%), then I can live with it. Anyhow, I cannot see any better solution (resources and performance) to generate the needed clock in Spartan 3E.

 

Do you think my requirements are met in this configuration?

 

Regards,

Paul


 

10% at 2.048 MHz is pretty close to a full clock cycle at 20 MHz.  So you could dispense

with the DCM's and just use fabric logic to generate the 2.048 MHz (average) rate using

something like direct digital synthesis (1 bit).  This is a tried an true method for baud

rate generators.  If you want to do a bit better on the output jitter you could always use

a single DCM to bump up the frequency of the synthesizer.  The problem with cascading

DCM's is that they can lose lock when there is too much jitter, so proving that this

works with a single device may not mean it works for all devices under all conditions.

 

-- Gabor

-- Gabor
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Instructor
Instructor
6,289 Views
Registered: ‎08-14-2007

Re: Cascade 2 x DCM. Input for the second one is CLKFX

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I posted this on comp.lang.verilog some time back.  It's a verilog module for

doing pretty much what you want.  It wouldn't be hard to implement in VHDL

if you prefer that.  Using this module with 20 MHz in, m = 256 and d = 625

would output 4.096 MHz.


This code uses DDS with a variable divisor to allow jitter free output
for integer division of the input frequency, and exact fractional
frequencies with the usual induced cycle jitter for other
frequencies.  The output is relatively square and must be less than
or equal to 1/2 the input frequency.  If you want to use the code
to generate a clock enable instead of a square wave, the
output rate can go up to the input frequency as noted below.

module freq_synth
(
  clk,
  clr,
  m,
  d,
  q
);

input clk;      // Frequency reference in
input clr;      // Asynchronous reset
input [15:0] m; // Frequency multiplier
input [15:0] d; // Frequency divider
output q;       // synthesized clock out

// This module takes the input reference frequency and
// generates an output frequency of m / 2d times that
// frequency.  d must be greater than or equal to m.
// For 200 MHz input, the maximum output frequency is
// 100 MHz (d == m).

reg q;
reg [17:0] a, b, diff;    // counters and comparators (2 extra bits)

always @*
  diff = b - a;  // keep track of difference

always @ (posedge clk or posedge clr)
if (clr)
  begin
    q <= 0;
    a <= 0;
    b <= 0;
  end
else
  begin
    a <= a + m;     // a counts up by multiplier (always)
    if (diff[17])   // if a gets ahead of b
      begin
        // count  up by divider value and toggle the output
        b <= b + d;
        // Instead of complementing q, for a clock enable you could
        // set q to 1 here and clear it otherwise:
        q <= !q;
      end
  end

endmodule

-- Gabor
Observer therealpaulie
Observer
6,258 Views
Registered: ‎11-18-2009

Re: Cascade 2 x DCM. Input for the second one is CLKFX

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Hi Gabor,

 

Thank you for your answer. I'll follow your suggestion.

I'm going to use a DCM to divide the clock with 25  and multiply with 32 (or 16) and then your DDS code. I think this way I'll get better results. I need +/-10% but I would like to get the best of it.

 

Regards,

Paul

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Observer sp_usr
Observer
216 Views
Registered: ‎10-16-2012

Re: Cascade 2 x DCM. Input for the second one is CLKFX

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Hi Austin,

I´m looking for the same information but for Spartan 6 devices and I just found this post.

Is it possible to cascade 2 DCM, being the CLK_IN input of the second one CLK_FX? Is it a recommended practice for S6? I found some information about adding PLL-s between to reduce jitter.

Thanks.

 

 

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