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Voyager
Voyager
3,063 Views
Registered: ‎02-10-2012

Clarification about OVERSAMPLING mode of ISERDESE2 in 7 Series FPGA

I was going through the UG471 (v1.3) October 31, 2012 to understand more about the OVERSAMPLING mode of ISERDESE2. My main aim is to use it for asynchronous oversampling . I find some conflicting information on Page 150. Could any one clarify this ?

 

The guid says :

 

The OVERSAMPLE mode is used to capture two phases DDR data. Figure 3-7 shows a more detailed logical representation of the ISERDESE2 and how data is captured on both the rising and falling edge of CLK and OCLK. As shown in Figure 3-7, there must be a 90°offset phase relationship between CLK and OCLK as the data is captured on both CLK and OCLK but is clocked out of the ISERDESE2 on the CLK domain. CLKDIV is not used in this mode. The only valid clocking arrangements for the OVERSAMPLE interface type are:
• CLK and CLKB are driven by a BUFIO. OCLKB is driven by a BUFIO that is phase shifted by 90°. The two BUFIOs are driven from a single MMCM.
• CLK and CLKB are driven by a BUFG. OCLKB is driven by a BUFG that is phase shifted by 90°. The BUFGs are driven from a single MMCM.

 

My question : The first part says there should be a 90 degrees offset btw CLK and OCLK. Later it says there should be a phase shift of 90 degrees for OCLKB!

Going by the parameters explained before CLK and CLKB are inverted to each other ( 180 degrees phase difference) and so should OCLK and OCLKB! .

 

Just wanted to clarify what is the correct settings? If my understanding is correct it shoul be something like this :

 

CLK : orininal 0 degrees phase shifted clock.

CLKB : 180 degrees phase shifted clock with respect to CLK

OCLK : 90 degrees phase shifted compared to CLK

OCLKB : 180 degrees phasse shift with respect to OCLK or 270 degrees phase shifted with respect to CLK

 

Please correct me if I am wrong.


Regards

Arvind

 

 

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1 Reply
Newbie fusion2012
Newbie
2,993 Views
Registered: ‎06-04-2013

Re: Clarification about OVERSAMPLING mode of ISERDESE2 in 7 Series FPGA

Your assumption about the clocks and phase are correct from what I have found.  You have to feed all four phases of the oversampling clock to the ISERDES block. The documentation is really bad for this mode. If you go back to the V6 documentation it is still bad but the picture describing how it works is a little better, although still not complete. 

 

Good luck!

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