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Visitor adrianjgp
Visitor
10,338 Views
Registered: ‎04-26-2012

Clock source in KC705 EVM

Hello, everybody.

I'm an electronic engineer student and I've worked with FPGA boards before. Nowadays I'm working on a Kintex-7 KC705 EVM but I am not familiar with differential signaling and I am stucked because I can not correctly configure my clock input although the "static logic" (fixed outputs) work well.

For my test, I'm just programming a LED counter using the GPIO LEDs 4 to 7 and I selected as my input clock the 200MHz System Clock Source SYSCLK. The "Master UCF Listing" in the EVM User's Guide shows that SYSCLK is a LVDS signal.

For my test, I did the following VHDL:

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

--
------------------------------------------------------------------------------------
--
--
entity blazetest is
    port
    (
        clk_p: in std_logic;
        clk_n: in std_logic;
        led_indic: out std_logic_vector(3 downto 0)
    );
end entity;
--
------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of blazetest is

signal clk: std_logic;


signal count: std_logic_vector(31 downto 0) := (others => '0');
signal count_led: std_logic_vector(1 downto 0) := (others => '1');
signal clear: std_logic := '0';

begin

    IBUFDS_inst : IBUFDS
    generic map (
        DIFF_TERM => TRUE, -- Differential Termination
        IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
        IOSTANDARD => "DEFAULT")
        port map (
        O => clk, -- Buffer output
        I => clk_p, -- Diff_p buffer input (connect directly to top-level port)
        IB => clk_n -- Diff_n buffer input (connect directly to top-level port)
    );
    
    count <= (others => '0') when (clear = '1') else std_logic_vector(unsigned(count) + 1) when rising_edge(clk);
    
    clear <= '1' when count = std_logic_vector(to_unsigned(200000000,32)) else '0';
    
    count_led <= std_logic_vector(unsigned(count_led) - 1) when rising_edge(clk);
    
    led_indic(2 downto 1) <= count_led;
    led_indic(3) <= '1';
    led_indic(0) <= '1';

end architecture;

And the UCF file (generated with the PlanAhead tool):

 


# PlanAhead Generated physical constraints

NET "clk_p" LOC = AD12;
NET "clk_n" LOC = AD11; # I added this line.

# PlanAhead Generated IO constraints

NET "clk_p" IOSTANDARD = LVDS;
NET "clk_n" IOSTANDARD = LVDS;

# PlanAhead Generated physical constraints

NET "led_indic[1]" LOC = G19;
NET "led_indic[0]" LOC = AE26;
NET "led_indic[2]" LOC = E18;
NET "led_indic[3]" LOC = F16;

# PlanAhead Generated IO constraints

NET "led_indic[3]" IOSTANDARD = LVCMOS15;
NET "led_indic[2]" IOSTANDARD = LVCMOS15;
NET "led_indic[1]" IOSTANDARD = LVCMOS15;
NET "led_indic[0]" IOSTANDARD = LVCMOS15;

 

I get no warnings or errors in the Implementation and Generation processes. When I run the application on the board, only the GPIO_LEDs 0 and 2 ligth up, but the others doesn't seem to work.

 

Am I rigth with the things I'm trying? What do I have to change or configure to use that clock input?

Thanks for your help.

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7 Replies
Xilinx Employee
Xilinx Employee
10,330 Views
Registered: ‎01-03-2008

Re: Clock source in KC705 EVM

I think that you meant that LEDs 3 and 0 are lighted while 1 and 2 are not. If you were to put a scope probe on LEDs 1 and 2 you should see a 100 MHz and 50 MHz waveform respectively.

You coding style does not match general conventions. While there is nothing wrong with the code, it makes it extremely hard to read. Specifically I am referring to your use of "when rising_edge" instead of process statements with " if rising_edge"
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Instructor
Instructor
10,329 Views
Registered: ‎08-14-2007

Re: Clock source in KC705 EVM

What you see doesn't make a lot of sense.  You are assigning '1' to LED's 0 and 3.  Normally a '1'

means turn the LED off.  So I would expect to see light on LED's 1 and 2, not 0 and 2.

 

Also you have two counters, one long one "count" which doesn't appear to be used at all

(did you look at the warnings from synthesis?) and another 2-bit counter that drives the

LEDs.  That 2-bit counter is running at the clock frequency, so you should not expect to

see the LED's blink.

 

-- Gabor

-- Gabor
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Xilinx Employee
Xilinx Employee
10,326 Views
Registered: ‎01-03-2008

Re: Clock source in KC705 EVM

Xilinx boards use an active high convention for LEDs and Switches.
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Visitor adrianjgp
Visitor
10,318 Views
Registered: ‎04-26-2012

Re: Clock source in KC705 EVM

Hi, Gabor. You make me notice I wrote a wrong logic. The "count" was to count for a second and trigger the second counter, like:

 

count_led <= std_logic_vector(unsigned(count_led) - 1) when (rising_edge(clk) and clear = '1');

 

I will test that on Monday on the board, but I repeat, this is just a clock test. My actual question is if I'm adequately using the differential clock source.

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Instructor
Instructor
10,310 Views
Registered: ‎08-14-2007

Re: Clock source in KC705 EVM

The instantiation of the IBUFDS looks fine.  You could also instantiate the BUFG that goes after

this, but it isn't necessary for a simple design that only runs the clock directly and not through

a DCM or PLL.  XST defaults to inserting BUFG on clock nets.  It will issue a warning if it has not

done so automatically.

 

-- Gabor

-- Gabor
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Visitor adrianjgp
Visitor
10,307 Views
Registered: ‎04-26-2012

Re: Clock source in KC705 EVM

Hello, everyone.

I corrected my counter logic, but I still don't get any visible effect on the board LEDs (they stay in their initial state). I still don't get any error in the Implementation and binary Generation stages.

Does anybody have a working sample ISE project for a Kintex evaluation board?

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Xilinx Employee
Xilinx Employee
10,300 Views
Registered: ‎01-03-2008

Re: Clock source in KC705 EVM

Please post the corrected HDL code.

 

There are several example designs posted on the KC705 pages. 

http://www.xilinx.com/kc705

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