09-10-2018 02:13 AM
I am developing a project based on Artix7, and for this project, I have a LVDS interface implemented in the FPGA, to interface with an ADC.
That ADC has a settable sample length, translating in a settable frame length (since samples are serial transmitted).
I wanted to configure the DATA_WIDTH of the ISERDESE2 that I use to the maximum possible sample length, and perform a partial readout in the case fewer bits are used. For instance assuming the ADC is up to 8 bits, having a DATA_WIDTH = 8, connecting Q1 to Q8 to signals.
In the case the ADC is set for 6 bits sampling, I planned to read only Q1 to Q6, after 6 bit clock periods.
This is not working, and the values I see using chip scope seem like new sampled data are presented on the ISERDESE2 outputs Qx only every DATA_WIDTH bit clock cycles.
Is it correct? Is it possible to readout Qx earlier than after DATA_WIDTH cycles?
I read ug471 related section, but I haven't found something stating this.
09-19-2018 01:11 PM
I have no progress on this point, and I can't find a clearer behavior description from datasheet and application note.
Is there someone on this forum that can help?
09-19-2018 02:05 PM
In this case the bit clock clocks in 8 bits, then CLK_DIV which is the bit clock /8 passes the 8 bit parallel data out?
In this case you will get part of the new sample and part of the old one depending on the allignment of the data coming out of the ISERDES.
there is no way to dynamically configure the data width.
Are you changing the clocking based on what the ADC is doing?
How do you clock the ISERDES?
Is the data rate always the same and just the sample resolution change?
Perhaps the best approach if the sample resolution is changing but the bits per second stays the same would be to take the 8 bit data and then use a 3rd clock (/6) to gear box it from 8 to 6 bits in the fabric.
The only issues here is that if you can't send some kind of training pattern from the ADC you will struggle to allign the data like you would with the bit slip.
09-20-2018 12:56 PM
@klumsde thanks for your reply.
In the case of 8 bits frameclock, the divclk is a division by 8 of the bit clock.
To willustrate, assuming bit clock is 240MHz, in 8 bits, divclk is 30MHz, in the case of 12 bits, divclk is 20MHz.
In the case of 8 bits, I see only new data at the output of ISERDESE only twice in 3 divclk cycles. And this is very repetitive.
Which means that no matter if divclk is 20MHz or 30MHz, the refresh rate of the ISERDES parallel output is 20MHz, corresponding to the ISERDES setting.
I am not changing the sampling rate of the ADC, which means the bit clock is not constant when resolution changes. So the datarate is linear with resolution.
I am also changing the ADC clocking frequency (independently of resolution setting).
I clock the ISERDES following the scheme described in XAPP524.
The only difference with XAPP524 is that I generate all divclk division factor with a dedicated BUFR for each and a mux to select the valid divclk depending on the current ADC resolution.
I was also considering a gearbox scheme if my approach is not working with ISERDESE. I just wanted to clarify ISERDESE behavior before implementing a gearbox just because of a misunderstanding. I have access to training patterns, so this could be feasible ( I already use the training patterns for bitslip).