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Explorer
Explorer
237 Views
Registered: ‎10-16-2018

DIFF_SSTL15 to TMDS_33

Hi , 

I am confronting "Conliting VCC voltages" in Bank 35 ,

so as solution to this error :

[DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 35. For example, the following two ports in this bank have conflicting VCCOs:
ddr3_sdram_ck_p[0] (DIFF_SSTL15, requiring VCCO=1.500) and sys_clock (LVCMOS33, requiring VCCO=3.300)

I changed the I/O std for ddr3_sdram_ck_p[0] from DIFF_SSTL15 to TMDS_33 .

The question is : What the consequences for this action I made ?

I attached a picture. thank you. 

DIFF_SSTL15 to TMDS_33.JPG
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1 Reply
Scholar dgisselq
Scholar
209 Views
Registered: ‎05-21-2015

Re: DIFF_SSTL15 to TMDS_33

@ahmed_alfadhel,

Based upon your other questions, you are struggling with a different problem from the one you are asking.  Since you are using the Arty A7 board, all of the pin locations and voltages are already fixed.  The consequence of changing them in the dialog box you are working with is that your design won't work.  The reason for your problem is not that you have the wrong voltage standard, but rather that you either have placed a pin definition on the wrong pin, or you have not defined a given pin.  Double check your pin assignments, and this error will go away and you will be able to assign your voltages to more reasonable values.

Dan