09-11-2017 07:28 PM
I have 7A200T device with 77,845,216 bits (9730652 bytes) configuration file size.
I am using Slave SelectMAP (8-bit bus width) configuration interface and an encrypted binary configuration image (size 9,730,652) generated by Vivado 2015.4.
For some reason I see the Done pin released after the 9,729,732 configuration byte instead of after the last 9,730,652 byte (920 configuration bytes earlier).
This is causing an issue for my design and I am wondering what could be the explanation for this.
09-11-2017 08:41 PM
What is the issue that you are seeing with your design?
Try the following command, regenerate the bitstream and let me know if this helps.
set_property BITSTREAM.STARTUP.DONE_CYCLE 6 [current_design]
Also, try using the latest version of Vivado for better results.
09-11-2017 09:00 PM
Thank you for trying to help.
The issue was that by default the IO outputs were enabled before (startup phase 5) the logic flip-flops (startup phase 6).
This was causing a CPU deadlock because of holding a wait state signal low (after phase 5) and not releasing it due to the late logic startup (phase 6).
Swapping the IO outputs and logic startup sequence phases fixed my issue.
I am still curious to know why the startup phase and Done goes high so early before the end of the configuration file.