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Visitor avi833
Visitor
4,817 Views
Registered: ‎06-09-2015

GTX GTHE3 CHANNEL TX direction. tx_usrclk_out output

i tried to implement TX direction on "v_smpte_uhdsdi_gtwiz" (from mange ip)

 

my ref clk gth_qpll0_ref_clk_p_in = 148.5Mhz

drpclk = 148.5Mhz

tx_mode = '01' - SD-SDI

tx_m_in = 1

gth_wiz_treset_all_in = asserted to '1' more then 1 cycle of drp clock

qpll0_lock = 1

 

 

but tx_userclk_out ouput is '0'!! - need to be 148.5Mhz

 

i dont why. if someone can help me with this. i will be more than happy [-:

 

 

 

 

 

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5 Replies
Xilinx Employee
Xilinx Employee
4,808 Views
Registered: ‎02-06-2013

Re: GTX GTHE3 CHANNEL TX direction. tx_usrclk_out output

Hi

 

I see that Qpll lock and gt reset done is not asserted in the simulations.

 

You need to simulate for longer time.

Regards,

Satish

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Visitor avi833
Visitor
4,802 Views
Registered: ‎06-09-2015

Re: GTX GTHE3 CHANNEL TX direction. tx_usrclk_out output

i simulate it for 5ms
and its ths same
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Xilinx Employee
Xilinx Employee
4,797 Views
Registered: ‎02-06-2013

Re: GTX GTHE3 CHANNEL TX direction. tx_usrclk_out output

Hi

 

Is this with the core generated test bench or your own.

Regards,

Satish

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Visitor avi833
Visitor
4,792 Views
Registered: ‎06-09-2015

Re: GTX GTHE3 CHANNEL TX direction. tx_usrclk_out output

my test bench.
very simple. only generator clk, rst, and tx_mode.

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Moderator
Moderator
4,714 Views
Registered: ‎02-16-2010

Re: GTX GTHE3 CHANNEL TX direction. tx_usrclk_out output

Please try simulating the example design to confirm the required reset procedure.
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