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Visitor vsheladiya
Visitor
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Registered: ‎12-19-2017

How to Delay Internal Signal?

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Hi,

 

I was going through 7-Series HDL library guide. I found that it has IDELAYE3/ODELAY3 to introduce a delay. But also it looks to me that it can only be used to delay input or output, not internal signals. Is it so?? If it is, then is there any other option to provide delay to internal signals?

 

Thanks,

Vijay

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Scholar dpaul24
Scholar
6,555 Views
Registered: ‎08-07-2014

Re: How to Delay Internal Signal?

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You can use IDELAY/ODELAY on internal signals.

 

But it seems like you did not pay attention to my post#2.

Every I/O block contains a programmable delay primitive called I/O-DELAY*. The placement of a DELAY module is fixed. So if you connect an internal signal to a DELAY module, have you considered the fact that you need to route your internal signal to and from the DELAY which is sitting on the edges of the chip? What do you think will be consequences on your timing analysis?

 

>>But what if I want to add delay to some internal signals which are belongs to internal logic and not going to or coming from out side of device.

Also I still don't understand this. An internal signal which belongs to internal logic also belongs to an internal clock domain. This internal signal must be in sync to that clock. Won't the use of a DELAY here make the internal signal go out of sync with your internal clock?

Or wait..... are you trying to use a delay module because you want to sync this internal signal with your internal clock?

 

I think  for getting a better answer, you need to explain why is it needed to delay the internal signal.

 

The primary purpose of IDELAY/ODELAY  modules is not to achieve what you want to do (adding small delays to internal signals). I am just giving you a premonition of can happen at the timing analysis stage.

 

 

 

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Scholar dpaul24
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Registered: ‎08-07-2014

Re: How to Delay Internal Signal?

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If it is, then is there any other option to provide delay to internal signals?

 

Why do you want to delay an internal signal?

Are you writing some *combinatorial only* logic?

 

If not (i.e. you are working with sequential logic) then this internal signal of yours must belong to some clock domain. Then this signal of yours must be transiting when the clock toggles. Adding an intentional delay to such a signal will be a serious mismatch.

So for sequential logic design, in order to delay an internal signal, just passing it through a flop will give it one cycle delay. For more delays. more flops.

 

As far as I know I/O-DELAY* Xilinx primitives are placed at the FPGA chip peripherals and they are used to add an additional delay to the data so that you do not violate setup/hold timing of the input register (for IDELAY) or the off chip synchronous element (for ODELAY). 

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Xilinx Employee
Xilinx Employee
4,868 Views
Registered: ‎08-01-2008

Re: How to Delay Internal Signal?

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You can use flop internally to delay signal by clock cycle. you can write FSM to latch signal based on some signal assertion conditions.

 

For example this process delay input by one clock cycle . Q and delayed_input can be internal signals

 

library ieee;
use ieee.std_logic_1164.all;

entity registers_1 is
port(C, Delayed_input  : in std_logic;
Q : out std_logic);
end registers_1;

architecture archi of registers_1 is
begin
process (C)
begin
if (C'event and C='1') then
Delayed_input <= input;
end if;
end process;
end archi;

Thanks and Regards
Balkrishan
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Visitor vsheladiya
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Registered: ‎12-19-2017

Re: How to Delay Internal Signal?

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Hi,

 

Thanks for your quick response..

 

One cycle of delay is too big for me, I need to add fine delay like IDELAYE3/ODELAYE3 introduces. Actually I need it for implementing DDR memory controller. So there apart from IOs, my internal control signals also needs some delays, that's why.

 

Thanks & Regards,

Vijay

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: How to Delay Internal Signal?

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You may use Xilinx MIG memory controller IPs. To implement delay refer this ARs
https://www.xilinx.com/support/answers/60802.html

check this related post
https://forums.xilinx.com/t5/Spartan-Family-FPGAs/iodelay2-min-max-delay/td-p/116418
Thanks and Regards
Balkrishan
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Scholar dpaul24
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Registered: ‎08-07-2014

Re: How to Delay Internal Signal?

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Yes in that case use the DELAY* primitives.

 

Actually I need it for implementing DDR memory controller.

All the best for timing analysis.

 

Recommendation is to use the Xilinx IP core as told above in order to avoid STA nightmares.

 

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Visitor vsheladiya
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Registered: ‎12-19-2017

Re: How to Delay Internal Signal?

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Hi Balkris,

 

My question is not about min/max delay values what IODELAY can introduce. Also I don't want to use MIG Memory Controller. I want to implement my own customized memory controller. So I wanted to know that apart from IOs, can I use IODELAY to introduce delay to my internal signal?

 

To make it more clear, lets say I have number of inputs and outputs in my core and also I have some internal logic. So using IDELAYE3, I can add delay to all my inputs, and using ODELAYE3, I can add delay to all my outputs. But what if I want to add delay to some internal signals which are belongs to internal logic and not going to or coming from out side of device.

 

Thanks & Regards,

Vijay

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Scholar dpaul24
Scholar
6,556 Views
Registered: ‎08-07-2014

Re: How to Delay Internal Signal?

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You can use IDELAY/ODELAY on internal signals.

 

But it seems like you did not pay attention to my post#2.

Every I/O block contains a programmable delay primitive called I/O-DELAY*. The placement of a DELAY module is fixed. So if you connect an internal signal to a DELAY module, have you considered the fact that you need to route your internal signal to and from the DELAY which is sitting on the edges of the chip? What do you think will be consequences on your timing analysis?

 

>>But what if I want to add delay to some internal signals which are belongs to internal logic and not going to or coming from out side of device.

Also I still don't understand this. An internal signal which belongs to internal logic also belongs to an internal clock domain. This internal signal must be in sync to that clock. Won't the use of a DELAY here make the internal signal go out of sync with your internal clock?

Or wait..... are you trying to use a delay module because you want to sync this internal signal with your internal clock?

 

I think  for getting a better answer, you need to explain why is it needed to delay the internal signal.

 

The primary purpose of IDELAY/ODELAY  modules is not to achieve what you want to do (adding small delays to internal signals). I am just giving you a premonition of can happen at the timing analysis stage.

 

 

 

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Xilinx Employee
Xilinx Employee
4,784 Views
Registered: ‎06-30-2010

Re: How to Delay Internal Signal?

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what sort of delay is needed, 10's of pS 100's??

If you are doing a customer memory controller is there a reason why you are not using MIG?

For the Delays there is a fabric in an out port that can be used, have a look at the DATAIN and DATAOUT ports:

"Data Input from the FPGA Logic - DATAIN
The DATAIN input is directly driven by the FPGA logic providing a logic accessible delay
line. The data is driven back into the FPGA logic through the DATA OUT port with a delay
set by the IDELAY_VALUE. DATAIN can be locally inverted. The data cannot be driven to
an IOB.
Data Output - DATAOUT
Delayed data from the two data input ports. DATAOUT can drive to either an ILOGICE2/
ISERDESE2 or ILOGICE3/ISERDESE2 block, directly into the FPGA logic, or to both."

From UG 471 page 117: http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf
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Visitor vsheladiya
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Registered: ‎12-19-2017

Re: How to Delay Internal Signal?

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Hi,

 

I think this would be good enough for me as of now. Thank you.

 

Thanks & Regards,

Vijay

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