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Explorer
Explorer
10,223 Views
Registered: ‎03-06-2014

How to bring an internal signal of a module into test bench ?

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Hello,

 

I am working on a design that a Linear Feedback Shift Register (LFSR) is providing a sigal for a module connected to nits output. Now, I am going to bring the LFSR signal into the Testbench and make a delay on one of its cycles and see its effect on the consequent module behavior. I am wondering a way to bring such a signal into the testbench as of my purpose.

 

Any kind help is cordially appreciated.

 

Regards,

 

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Adventurer
Adventurer
2,095 Views
Registered: ‎08-30-2018

Re: How to bring an internal signal of a module into test bench ?

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Hi,

 

Simply you can do it in VHDL/Verilog. Just connect an inter-module signal to the top file and then constrain this signal as a port in your UCF/XDC (depending of what you use, ISE or Vivado) file. Please note that we will have only 1 cnstraint file for the design which appears for the TOP file except you do a block design using Xilinx IPs that will automatically an XDC file each IP used in the design.

 

Good luck,

 

8 Replies
Voyager
Voyager
10,200 Views
Registered: ‎04-21-2014

Re: How to bring an internal signal of a module into test bench ?

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Is there a reason you cannot route it out of your DUT via another port? 

 

Or are you just trying to see a signal in a simulaton waveform viewer, just browse your hiearcy and add the signal to the waveviewer.

 

Or, in VHDL 2008 you can use something like this in your testbench:

 

alias wQspy is << signal MyMd_DUT.SomeOther_Mod_U0.wQ :  std_logic_vector(1 downto 0) >>; -- VHDL 2008

 

In order for this to work, you'll have to do something like this in your tcl console:

 

#enable VHDL 2008 for my test bench

set_property FILE_TYPE "VHDL 2008" [get_files MyMdTop_tb.vhd]

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Instructor
Instructor
10,186 Views
Registered: ‎08-14-2007

Re: How to bring an internal signal of a module into test bench ?

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You can also access signals anywhere in the hierarchy from a Verilog test bench.  What is your preferred design entry method?

-- Gabor
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Explorer
Explorer
10,183 Views
Registered: ‎03-06-2014

Re: How to bring an internal signal of a module into test bench ?

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Hi @gszakacs,

 

Thanks for your reply. I know PORT MAP and its utilization but I am not about to see the signal in the output window. I know that it is possible to see any signal anywhere in top module. Indeed, the LFSR is producing a signal and feeds it into another module. I am wondering to be able to control this signal manually at the testbench and create a delay in it and see how it affects the functionality of the sequence module.

Regards,

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Explorer
Explorer
10,180 Views
Registered: ‎03-06-2014

Re: How to bring an internal signal of a module into test bench ?

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Hi @morgan198510,

 

Thank you for your reply. Indeed I know that it is possible to route out a signal in an output port in DUT and monitor it in the waveform or, any signal anywhere in the DUT can be directly monitored from the hierarchy window in simulation wizard. 

As of my goal, indeed, the LFSR is generating a signal and feeds in into another module. I am wondering to be able to control this signal manully in my testbench and add a delay to it and see its effect on the next module behavior. Is it possible to control an internal signal in the testbench??

 

I also tried your suggestion, but it did not work and I got the following error message:

 

Command>#enable VHDL 2008 for my test bench

Command>set_property FILE_TYPE "VHDL 2008" [get_files tb2_top.vhd]

invalid command name "get_files"

 

Thanks,

 

 

 

 

 

 

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Voyager
Voyager
10,177 Views
Registered: ‎04-21-2014

Re: How to bring an internal signal of a module into test bench ?

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@msdarvishi wrote:

Hi @morgan198510,

 

Thank you for your reply. Indeed I know that it is possible to route out a signal in an output port in DUT and monitor it in the waveform or, any signal anywhere in the DUT can be directly monitored from the hierarchy window in simulation wizard. 

As of my goal, indeed, the LFSR is generating a signal and feeds in into another module. I am wondering to be able to control this signal manully in my testbench and add a delay to it and see its effect on the next module behavior. Is it possible to control an internal signal in the testbench??

 

I also tried your suggestion, but it did not work and I got the following error message:

 

Command>#enable VHDL 2008 for my test bench

Command>set_property FILE_TYPE "VHDL 2008" [get_files tb2_top.vhd]

invalid command name "get_files"

 

Thanks,

 

 

 

 

 

 


Which version of VIvado are you using?

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Explorer
Explorer
10,173 Views
Registered: ‎03-06-2014

Re: How to bring an internal signal of a module into test bench ?

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I am using ISE 14.7 and my targeted FPGA is Virtex-5 (XC5VLX50T).

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Voyager
Voyager
10,166 Views
Registered: ‎04-21-2014

Re: How to bring an internal signal of a module into test bench ?

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@msdarvishi wrote:

I am using ISE 14.7 and my targeted FPGA is Virtex-5 (XC5VLX50T).


Okay, then you can't use VHDL 2008.

 

Route your ports to the top level (VHDL), pick your signals for your waveform viewer by navigating your hiearchy, or swtich to a different HDL that supports spying signals down into the heiarchy.  Depending on your simulator, you may be able to use simulator scripting to acomplish what you want, too, but I don't personally like doing that.

 

Another option is to buy a Nexys 4 from Digilent and get Vivado.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Adventurer
Adventurer
2,096 Views
Registered: ‎08-30-2018

Re: How to bring an internal signal of a module into test bench ?

Jump to solution

Hi,

 

Simply you can do it in VHDL/Verilog. Just connect an inter-module signal to the top file and then constrain this signal as a port in your UCF/XDC (depending of what you use, ISE or Vivado) file. Please note that we will have only 1 cnstraint file for the design which appears for the TOP file except you do a block design using Xilinx IPs that will automatically an XDC file each IP used in the design.

 

Good luck,