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Explorer
Explorer
15,243 Views
Registered: ‎03-06-2014

How to check for two signal transitions in VHDL?

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Hello,

 

I am working on a design that I need to write an expression in VHDL to translate this statement :

"If the rising edge of CLK signal occurred and rising edge of another signal occured..., do something "

 

I wrote the following code :

 

process (clk, locked_sig_s, enable, latched_output, S1, S2, S3)

 

begin

        if (locked_sig_s = '1' and enable = '1') then
                if (RISING_EDGE(clk) then
                         if (RISING_EDGE(latched_output)) then


                                       S1 <= clk - latched_output_sig;

                         elsif (FALLING_EDGE(latched_output_sig(0))) then

                                       S2 <= latched_output_sig - clk;

 

...

 

 

I got the following error :

 

ERROR:Xst:827 - "/export/tmp/darvishi/xilinx/BASIC_FPGA_TDC_Design_Me_part_by_part/TDC_Complete_with_Renaud_PLL_with_LFSR_Comparison_New_Technique_Aug_17/observer.vhd" line 94: Signal S2 cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
-->

 

I know that:

 

Writing in this style means that we must assort a D-FlipFlop being sensitive to two transitions that is not possible in FPGA hardware... But I am wondering there is way to do the statement in VHDL?

 

Thank in advance for your help

 

Regards,

 

 

 

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1 Solution

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Adventurer
Adventurer
3,038 Views
Registered: ‎08-30-2018

Re: How to check for two signal transitions in VHDL?

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Hi,

 

If your signals are clocks you may do it with a VHDL code. but if your signals are global signals and do not use dedicated routes in the fabric and are not properly buffered, that's another story and it won't be as easy as clock signals. Note that the global signals timing closure varies too much with PVT. Just do a simple implementation and look at timing analysis report to see the results varying implementation by implementation !! That sucks, I know but it is how it works inside the FPGA. Look here it may give you a hint.

 

Hope it helps...

 

9 Replies
Voyager
Voyager
15,231 Views
Registered: ‎04-21-2014

Re: How to check for two signal transitions in VHDL?

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You can model more things in VHDL than you can synthesize. 

 

For example, your code.

 

Another example is wait for 3.456 nS;  This can be simulated but not synthesized.

 

What is the goal of this problem?  Sounds like this is for a class.  For a class, you might just want to model two D-flip flops, both initialized to 0, with their D inputs tied high.  Tie your clock to one of the DFF's clock input, and your other signal to the other DFF's clock input.  AND the two Q outputs.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Scholar austin
Scholar
15,228 Views
Registered: ‎02-27-2008

Re: How to check for two signal transitions in VHDL?

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m,

 

You have two clocks, clock1, and the signal you want to detect the rising edge on is clock2.

 

Two DFF, each has a clock, clock1 for DFF1, clock2 to DFF2.  Each DFF has its D input tied high.  They both get reset when it is time to look for another set of rising edges.


The Q outputs get AND'ed together to form the signal to indicate the edges have occurred.

 

Generally, this is not a good idea of how to design a synchronous circuit (using multiple clocks, especially asynchrounous ones, is vey bad practice due to metastability).

 

What are you trying to accomplish?

 

Using one clock, and the other signal as an enable to one DFF:  perhaps that also does what you need?  What is so important about the rising edge of the signal?  Isn't all you need to know is that the signal was high when a clock occurred?  Is that not equivalent?  If not, what else did you think you required (as that is all that you get even using two DFF and two clocks with the AND gate).

 

 

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Observer scottconnors
Observer
15,210 Views
Registered: ‎06-25-2014

Re: How to check for two signal transitions in VHDL?

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I'm very confused by the code, but what you say you want to do is very straight-forward.  Your statement was:

 

I am working on a design that I need to write an expression in VHDL to translate this statement :

"If the rising edge of CLK signal occurred and rising edge of another signal occured..., do something "

 

To do this in VHDL is a simple matter.  Assuming you have a signal, let's call it "sig", and a clock, let's call it "clk", you can do the following.  Note that only a clock signal should be used in a rising_edge or falling_edge statement, otherwise you will infer clocks all over your design and it will become a big mess.  Also, if you are only sensitive to clk changing, you don't need to include every possible signal in your sensitivity list.  This can cause delays during simulations, but is ignored by synthesis.

 

Here is the code you are looking for:

 

process(clk) is
   variable sigDel : std_logic;                 -- could also use a signal
begin
   if rising_edge(clk) then
      if sig = '1' and sigDel = '0' then        -- detect rising edge of sig
           do something cool;               
      elsif sig = '0' and sigDel = '1' then     -- or detect falling edge of sig if needed
           do something else;
      else
           may not need this;
      end if;
      
      sigDel := sig;                            -- register sig for edge detection use
                                                -- register variables after they are used
   end if;
end process;

Don't treat  VHDL like a programming language.  Think of the hardware that is created and use that knowledge.

 

Scott

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Explorer
Explorer
15,154 Views
Registered: ‎03-06-2014

Re: How to check for two signal transitions in VHDL?

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Thanks for your wise and good explanation. You know my purpose is :

 

I have a clock signal of 400 MHz and I have a signal coming from a Linear Feedback Shift REgister (LFSR) that is not a regular signal like clock. My goal is to find the delay between the rising edge of the clock signal and "any transition" in the signal coming from LFSR. If these two values are too close, it means that the timing error has occured in the signal coming from LFSR. That's why I tried to go for that implementation that did not work !

 

Kind helps are cordially appreciated.

 

Regards,

 

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Voyager
Voyager
15,116 Views
Registered: ‎04-21-2014

Re: How to check for two signal transitions in VHDL?

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@msdarvishi wrote:

...

 

I have a clock signal of 400 MHz and I have a signal coming from a Linear Feedback Shift REgister (LFSR) that is not a regular signal like clock. My goal is to find the delay between the rising edge of the clock signal and "any transition" in the signal coming from LFSR. If these two values are too close, it means that the timing error has occured in the signal coming from LFSR. That's why I tried to go for that implementation that did not work !

 

...


Is the LFSR also clocked by the 400 MHz clock?  And are you trying to measure the delay in clock periods, or fractions of a clock period.  If the later, you're going to have trouble. 

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Explorer
Explorer
15,074 Views
Registered: ‎03-06-2014

Re: How to check for two signal transitions in VHDL?

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Yes, the LFSR is clocked with 400MHz as well. At any clock transition, I would like to measure the delay between its transition and the transition of the signal coming from LFSR. Since the signal of the LFSR only changes at clock rising edges, indeed the measurement would be performed during a clock cycle, but I do not know how to do it!?

 

Thanks

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Voyager
Voyager
15,043 Views
Registered: ‎04-21-2014

Re: How to check for two signal transitions in VHDL?

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Okay, then, you can do it.  You'll be able to count the number of clocks between transitions. 

 

For example, to count rising edge to rising edge clocks, do something like this (not syntax checked):

 

  use IEEE.numeric_std.all;

  ...

  process(iCLK)
  begin
    if rising_edge(iCLK) then
      if(iRST = '1')then
        cnt       <= 0; -- integer range 0 to kMAX_CNT, a constant
        re2re     <= 0; -- integer range 0 to maximum expected value, rising edge to rising_edge
        start_cnt <= 0; -- integer range 0 to kMAX_CNT
        sig_d1    <= '0';
      else
        if(cnt = kMAX_CNT) then
          cnt <= 0;
        else
          cnt <= cnt + 1; -- free running clock counter
        end if;
        sig_d1 <= iSig; -- delay
        if(sig_d1 = '0' and iSig = '1') then
          re2re     <= cnt - start_cnt;
          start_cnt <= cnt;
        end if;
    end if;
  end process;

  oRE2RE <= std_logic_vector(to_unsigned(re2re,oRE2RE'length));

 

If you do not understand that, you should probably take some VHDL training. 

 

Disclaimer:  The above code may have syntax errors.  It was not tested.  Likely to be off by 1 on the re2re.

 

Good luck, and I hope this helps.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Voyager
Voyager
14,856 Views
Registered: ‎04-21-2014

Re: How to check for two signal transitions in VHDL?

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@msdarvishi, did you find the post helpful?

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***
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Adventurer
Adventurer
3,039 Views
Registered: ‎08-30-2018

Re: How to check for two signal transitions in VHDL?

Jump to solution

Hi,

 

If your signals are clocks you may do it with a VHDL code. but if your signals are global signals and do not use dedicated routes in the fabric and are not properly buffered, that's another story and it won't be as easy as clock signals. Note that the global signals timing closure varies too much with PVT. Just do a simple implementation and look at timing analysis report to see the results varying implementation by implementation !! That sucks, I know but it is how it works inside the FPGA. Look here it may give you a hint.

 

Hope it helps...