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Explorer
8,911 Views
Registered: ‎03-06-2014

## How to decrease clock frequency of DCM?

Hello everybody,

I am using the DCM primitive at Virtex-5 with 64MHz internal CLK_IN and I have a counter using IP cores that counts to 61A with that frequency. I manipulated UCF to lead the output of my top module into the LEDs on Xilinx Gensys Virtex-5 Board including XC5VLX50T to be able to see the counting operation on LEDs. But since the clock frequency is high (64MHz) I see nothing. I triedto decease the DCM input clock frequency but the minimum is 64MHz that is divided by 2. Can anyone assist me how to overcome this problem?

Thanks,

1 Solution

Accepted Solutions
751 Views
Registered: ‎08-30-2018

## Re: How to decrease clock frequency of DCM?

Hi,

In your counter, 61A = 1562 ~ 1.5 KB --- > Frenquncy rate = 1562 Hz ~ 1.562 KHz

min DMC CLK_IN = 64MHz = 64000 KHz

Number of LED blinks = 64000KHz/1.562KHz ~ 40973   ---> Too much high to be watchdog on a simple LED!

0d =  Decimal

0b = Binary

Instead, put a counter that counts until 0d64,000,000 = 0x3D09000 = 0b11110100001001000000000000 ---- > So, you have to design a 26-bits counter.that can be achieved simply with FFs.

So, the LED bloinkingrate will be 64000KHz / 0d64,000,000 = 1 Hz ---- > You can visuallly observe the on/off toggling of the LED.

Indeed, by using a higher bit counter, you can achieve the lower frequency, you did not decrease that frequency just allowed a more relax counter to counter to higher values !

hope it helps...

Daryon

4 Replies
Xilinx Employee
8,899 Views
Registered: ‎02-06-2013

## Re: How to decrease clock frequency of DCM?

Hi

You can use Modulo counter to divide the clock generated by DCM to derive lower frequency clocks.

Have a look at below links

http://electronics.stackexchange.com/questions/61422/how-to-divide-50mhz-down-to-2hz-in-vhdl-on-xilinx-fpga

http://forums.xilinx.com/t5/Virtex-Family-FPGAs/Virtex-5-DCM-output-to-1MHz/td-p/172786

Regards,

Satish

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Xilinx Employee
8,882 Views
Registered: ‎08-01-2012

## Re: How to decrease clock frequency of DCM?

Please refer DCM Switching Characteristics Table 76 (page 57) in the below Virtex-5  data sheet http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf.

As per that 64 M HZ input clock supported in low frequency DLL mode. High frequency DLL mode does not support 64 M HZ (Please note that DFS modes supports).

What DCM modes are you using? I think you are using high frequency mode and DLL outputs. Please check your case against that above limitation. If that is the case no need to reduce the input clock frequency. Simply use low frequency mode for DCM and verify required outputs are coming or not.

FYI: The below is additional generic information to debug clocking problems

http://www.xilinx.com/support/troubleshoot/clocking_debug.htm

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

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Historian
8,826 Views
Registered: ‎02-25-2008

## Re: How to decrease clock frequency of DCM?

@msdarvishi wrote:

Hello everybody,

I am using the DCM primitive at Virtex-5 with 64MHz internal CLK_IN and I have a counter using IP cores that counts to 61A with that frequency. I manipulated UCF to lead the output of my top module into the LEDs on Xilinx Gensys Virtex-5 Board including XC5VLX50T to be able to see the counting operation on LEDs. But since the clock frequency is high (64MHz) I see nothing.

Why not monitor the LED signals on an oscilloscope? You won't see the LED blink but you'll see the drive signal toggle.

----------------------------Yes, I do this for a living.
752 Views
Registered: ‎08-30-2018

## Re: How to decrease clock frequency of DCM?

Hi,

In your counter, 61A = 1562 ~ 1.5 KB --- > Frenquncy rate = 1562 Hz ~ 1.562 KHz

min DMC CLK_IN = 64MHz = 64000 KHz

Number of LED blinks = 64000KHz/1.562KHz ~ 40973   ---> Too much high to be watchdog on a simple LED!

0d =  Decimal

0b = Binary

Instead, put a counter that counts until 0d64,000,000 = 0x3D09000 = 0b11110100001001000000000000 ---- > So, you have to design a 26-bits counter.that can be achieved simply with FFs.

So, the LED bloinkingrate will be 64000KHz / 0d64,000,000 = 1 Hz ---- > You can visuallly observe the on/off toggling of the LED.

Indeed, by using a higher bit counter, you can achieve the lower frequency, you did not decrease that frequency just allowed a more relax counter to counter to higher values !

hope it helps...

Daryon