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Highlighted Adventurer
253 Views
Registered: ‎10-16-2018

## How to get a low clocking rate by ARTY 7 ?

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Hi ,

I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture !

What are the other choices I have in order to achieve the output of LFSR at the low rate that I want ?

I read about delays in FPGA , but I found delays are not synthesized in FPGA !

Looking for your help,

Thanks

1 Solution

Accepted Solutions bruce_karaffa
Scholar
111 Views
Registered: ‎06-21-2017

## Re: How to get a low clocking rate by ARTY 7 ?

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There are some problems in your code.  First, you have a clocked process that has a great deal of code outside for the

`      if(rising_edge(i_clk)) then...     end if;`

construct.  Exceot for an asynchronous reset, everything in the process should be between this if and end if.   The test for i_en should be inside of the clocked part of the process as well as the part where you increment the counter.   Test for maxcount with an if statement, not a WHILE loop.  See if this process does what you want:

```  LFSR_proc: process(i_clk)
begin

if (i_en = '1') then
if(rising_edge(i_clk)) then          i_en <= not i_en;
r_lfsr(2) <= r_lfsr(0) xor r_lfsr(1);
r_lfsr(1) <= r_lfsr(2);
r_lfsr(0) <= r_lfsr(1);      if (counter <= maxcount) then            counter <= counter + 1;     else          counter <= 0;      end if;
end if;
end process LFSR_proc;```

What is the purpose ofthe counter?  It has no effect on the output of the entity.  If you want to use it to control i_en, you need a test like:

`if counter = (maxcount -1) then  i_en <= '1';else  i_en<='0';end if;`

Be sure to put this inside the rising_edge if statement.

8 Replies Xilinx Employee
225 Views
Registered: ‎03-07-2018

## Re: How to get a low clocking rate by ARTY 7 ?

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Hello @ahmed_alfadhel

I beleive you can use clk_wiz to get lowest possible frequency and then use counter for dividing minimum clock of clk_wiz to get your required clock.

Although this method is not efficient but I cannot think of any other way to do it.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
------------------------------------------------------------------------------------------------------------------------------------------------- Moderator
222 Views
Registered: ‎08-08-2017

## Re: How to get a low clocking rate by ARTY 7 ?

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Use the  CLKOUT4_CASCADE = TRUE functionality in the clocking wizard.

When CLKOUT4_CASCADE = TRUE, MMCM_FOUTMIN is 0.036 MHz. i.e 36KHz,

You can derive the 40Khz with proper settings of diver for CLOKOUT4 and CLOCKOUT6,  then use the devide by 5 counter logic to derive the 8Khz or Use the BUFR primitive and set the BUFR_divide attribute to 5.

BUFR is documented in below user guide.

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug953-vivado-7series-libraries.pdf

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
------------------------------------------------------------------------------------------------------------------------------- Adventurer
203 Views
Registered: ‎10-16-2018

## Re: How to get a low clocking rate by ARTY 7 ?

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Hi @pthakare ,

I set CLKOUT4_CASCADE = TRUE , but still cannot set clk_out3 to 0.036 MHz .

Kindly , could you elaborate more how to implement your idea ?

Kindly see the attached picture.

Thanks. Moderator
196 Views
Registered: ‎08-08-2017

## Re: How to get a low clocking rate by ARTY 7 ?

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You will not be able to directly set the 36Khz.

The significance of CLKOUT4_CASCADE  is  , it Cascades the output divider (counter) CLKOUT6 into the input of the CLKOUT4 divider for an output
clock divider that is greater than 128, effectively providing a total divide value of 16,384.

Minimum VCO frequency is  600.00 MHz, so the MMCM_FOUTMIN is 600/16384  = 0.036Mhz.

Consider below example , Input is 100Mhz, M =10 , so the VCO frequency = 1000Hz

the CLOCKOUT4 i. ckkout5 = 1000/16384 = 0.610 Mhz -------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
------------------------------------------------------------------------------------------------------------------------------- Adventurer
166 Views
Registered: ‎10-16-2018

## Re: How to get a low clocking rate by ARTY 7 ?

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Hi @bpatil :

I added enable signal (i_en) , which is controlled by a counter. As shown in my code below :

```-- Library's
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LFSR3 is
Port (
i_clk           : in  std_logic;
o_lsfr          : out std_logic_vector (2 downto 0)
-- i_en            : in  std_logic
);
end LFSR3;

architecture Behavioral of LFSR3 is

signal i_en    : std_logic := '1';
signal r_lfsr	: std_logic_vector(2 downto 0) := "100";
constant maxcount  : integer := 625;
signal counter : unsigned(9 downto 0) := to_unsigned(0, 10);

begin

o_lsfr <= r_lfsr;

LFSR_proc: process(i_clk)
begin
counter <= (others => '0');
i_en <= not i_en;
if (i_en = '1') then
if(rising_edge(i_clk)) then

r_lfsr(2) <= r_lfsr(0) xor r_lfsr(1);
r_lfsr(1) <= r_lfsr(2);
r_lfsr(0) <= r_lfsr(1);
end if;

else
-- line 75 (the error)
freq_8kHz: while (counter <= maxcount) loop
counter <= counter + 1;
end loop freq_8kHz;
end if;
end process LFSR_proc;

end Behavioral;```

And , when I run synthesized an error appeared :

"[Synth 8-3380] loop condition does not converge after 2000 iterations ["d:/Users/dell/Vivado_projects/LFSR2/LFSR2.srcs/sources_1/bd/LFSR/ipshared/4f95/src/LFSR3.vhd:75]"
I have pointed to the error location in my code (line 75) . So plz , could you tell me why my loop seems to be infinite (does not converge) !?

Thanks. Xilinx Employee
142 Views
Registered: ‎03-07-2018

## Re: How to get a low clocking rate by ARTY 7 ?

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Hello @ahmed_alfadhel

In your code, you are using enable signal generated by counter and counter is inside of same code.

Your initial value of i_en signal is also undefined; so if (i_en = '1') will never get valid at start.

Better and simple appraoch will be create separate code for counter and LFSR; then combine them in single top module in structural coding style. I believe this will simplify your coding for now. Although this is not the best way of coding but for your current requirement it seems simplified method to implement your design.

Regards,
Bhushan

-------------------------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
------------------------------------------------------------------------------------------------------------------------------------------------- bruce_karaffa
Scholar
112 Views
Registered: ‎06-21-2017

## Re: How to get a low clocking rate by ARTY 7 ?

Jump to solution

There are some problems in your code.  First, you have a clocked process that has a great deal of code outside for the

`      if(rising_edge(i_clk)) then...     end if;`

construct.  Exceot for an asynchronous reset, everything in the process should be between this if and end if.   The test for i_en should be inside of the clocked part of the process as well as the part where you increment the counter.   Test for maxcount with an if statement, not a WHILE loop.  See if this process does what you want:

```  LFSR_proc: process(i_clk)
begin

if (i_en = '1') then
if(rising_edge(i_clk)) then          i_en <= not i_en;
r_lfsr(2) <= r_lfsr(0) xor r_lfsr(1);
r_lfsr(1) <= r_lfsr(2);
r_lfsr(0) <= r_lfsr(1);      if (counter <= maxcount) then            counter <= counter + 1;     else          counter <= 0;      end if;
end if;
end process LFSR_proc;```

What is the purpose ofthe counter?  It has no effect on the output of the entity.  If you want to use it to control i_en, you need a test like:

`if counter = (maxcount -1) then  i_en <= '1';else  i_en<='0';end if;`

Be sure to put this inside the rising_edge if statement. Adventurer
92 Views
Registered: ‎10-16-2018

## Re: How to get a low clocking rate by ARTY 7 ?

Jump to solution

Thank you @bruce_karaffa ,

for your effective notes.

My LFSR is working now correctly at 8 kHz according to thw simulation and implementation on ARTY 7.

I attached the code and a snapshot for the simualtion.

Thank you @bpatil @pthakare .

My best Regards to you.

```----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/22/2019 03:39:00 PM
-- Design Name:
-- Module Name: LFSR3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

-- Library's
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.math_real.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity LFSR3 is
Port (
i_clk           : in  std_logic;
o_lsfr          : out std_logic_vector (2 downto 0)
-- i_en            : in  std_logic
);
end LFSR3;

architecture Behavioral of LFSR3 is

signal r_lfsr	: std_logic_vector(2 downto 0) := "100";
constant maxcount  : integer := 625;

begin

o_lsfr <= r_lfsr;

LFSR_proc: process(i_clk)
variable i_en    : std_logic := '0';
variable counter2 :unsigned(9 downto 0) := to_unsigned(0, 10);
begin

if(rising_edge(i_clk)) then

if(i_en = '1')  then
-- rubish of hops
r_lfsr(2) <= r_lfsr(0) xor r_lfsr(1);
r_lfsr(1) <= r_lfsr(2);
r_lfsr(0) <= r_lfsr(1);

counter2 := (others => '0');
i_en := '0';

elsif(counter2 /=(maxcount - 1)) then

counter2 := counter2 +1;

else
i_en := '1';
end if;

end if;
end process LFSR_proc;

end Behavioral;```