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Observer kritika117
Observer
1,136 Views
Registered: ‎03-07-2018

How to reduce delay while reading from BRAM?

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Attached is a simulation waveform for writing and reading from BRAM. We are using simple dual port RAM where we are using WRITE_FIRST mode for writing in port A and READ_FIRST for reading from port B. There is a delay in output data while reading. Data at output appears on the next read enable signal. Please see the simulated waveforms in which input and output are of 8-bit. Can anyone please help us.

 

 

1.png

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Community Manager
Community Manager
1,567 Views
Registered: ‎08-08-2007

Re: How to reduce delay while reading from BRAM?

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Are you using the optional output register? 

Figure 1-5: Block RAM Logic Diagram (One Port Shown) of http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf shows the EN is used on the Output Regiser for the EN would need to be high for two clock cycles for the data to appear on the output port.

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6 Replies
Community Manager
Community Manager
1,568 Views
Registered: ‎08-08-2007

Re: How to reduce delay while reading from BRAM?

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Are you using the optional output register? 

Figure 1-5: Block RAM Logic Diagram (One Port Shown) of http://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf shows the EN is used on the Output Regiser for the EN would need to be high for two clock cycles for the data to appear on the output port.

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Observer kritika117
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1,056 Views
Registered: ‎03-07-2018

Re: How to reduce delay while reading from BRAM?

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Thanks for replying.

 

I am not using any output register. Actually, the enable signal for port B is coming from an another ip and it is on for only one clock cycle. How to solve this?

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Moderator
Moderator
1,045 Views
Registered: ‎04-18-2011

Re: How to reduce delay while reading from BRAM?

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Despite it's name, READ_FIRST is a write mode. 

So data previously stored at the write address appears on the output
latches, while the input data is being stored in memory (read before write). The waveforms
in figure correspond to latch mode when the optional output pipeline register is not used.

 

forum_read_first.PNG

 

Maybe the UG gives a hint

 

When one port performs a write operation, the write operation succeeds; the other
port can reliably read data from the same location if the write port is in READ_FIRST
mode. DATA_OUT on both ports then reflects the previously stored data.
If the write port is in either WRITE_FIRST or in NO_CHANGE mode, then the
DATA_OUT on the read port would become invalid (unreliable). The mode setting of
the read-port does not affect this operation.

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Observer kritika117
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Registered: ‎03-07-2018

Re: How to reduce delay while reading from BRAM?

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Thanks a lot for this information.

 

But, if you see the attached simulation waveforms, I am not writing and reading simultaneously. Firstly, numbers are stored in BRAM through dina pin and then enable pin of port A is made zero. After disabling the port A, reading from port B is started. So, it should not give any invalid data. My concern is the delay of two read clocks which I am getting at the output.

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Moderator
Moderator
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Registered: ‎04-18-2011

Re: How to reduce delay while reading from BRAM?

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I wonder if you have a demo board you could try on? It would be good to correlate the simulation with hardware in case the simulation model is not correct.
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Observer kritika117
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Registered: ‎03-07-2018

Re: How to reduce delay while reading from BRAM?

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Thank you so much, your answer helped me.

 

In latch mode, the read operation uses one clock edge. And when using the output register, the read operation takes one extra latency cycle.

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