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Contributor
Contributor
1,722 Views
Registered: ‎10-03-2016

IBUFGDS is removed from vivado tool, why?

IBUFGDS is removed from vivado tool why? then what is the replacement for this?

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6 Replies
Xilinx Employee
Xilinx Employee
1,709 Views
Registered: ‎08-01-2008

Re: IBUFGDS is removed from vivado tool, why?

@subashrajam

Can you please elaborate more . what do you mean by removed my vivado tools

Check this guide for usage

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
1,704 Views
Registered: ‎09-20-2012

Re: IBUFGDS is removed from vivado tool, why?

Hi @subashrajam

 

You should use IBUFDS instead.

 

Check this thread for similar discussion https://forums.xilinx.com/t5/Implementation/IBUFGDS-gt-IBUFDS-Unisim-Transformation/td-p/509743

Thanks,
Deepika.
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Contributor
Contributor
1,668 Views
Registered: ‎10-03-2016

Re: IBUFGDS is removed from vivado tool, why?

I am referring xapp524 reference design where IBUFGDS is used in the VHDL code in the place of the differential clock pair. But I want Verilog code. So I am rewriting the VHDL code into Verilog code the meantime I searched in the tool template tab where it is not found. This is my problem. So what to do?

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Moderator
Moderator
1,656 Views
Registered: ‎09-18-2014

Re: IBUFGDS is removed from vivado tool, why?

Subashrajam,

 

Why not just use the regular IBUFDS as it is used in the XAPP524 diagrams for the design clocking structure? Just make sure the rest of the design in local. Or if you have to have the clock be global just append a BUFG to the IBUFDS. Vivado infers IBUFGDS and IBUFDS as the same to reduce complexity. To make the signal a global clock is to use a BUFG on the input clock line. 

 

Regards,

T

 

 

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Moderator
Moderator
1,648 Views
Registered: ‎04-18-2011

Re: IBUFGDS is removed from vivado tool, why?

As @vemulad points out. 

IBUFGDS is a construct that implies a direct connection from the Clock Capable pin to the clocking network. 

Perhaps it was needed in the past to guide the tools but the DRC capabilities in Vivado are able to determine valid clock capable pins. 

In this case you can just use an IBUFDS and lock it to a clock capable IO and this will work. 

 

Keith 

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Visitor xlx
Visitor
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Registered: ‎03-01-2013

Re: IBUFGDS is removed from vivado tool, why?

use IBUFDS + BUFG

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