01-22-2018 02:49 AM - edited 01-22-2018 03:00 AM
Can you please elaborate more . what do you mean by removed my vivado tools
Check this guide for usage
01-22-2018 02:59 AM - edited 01-22-2018 03:01 AM
You should use IBUFDS instead.
Check this thread for similar discussion https://forums.xilinx.com/t5/Implementation/IBUFGDS-gt-IBUFDS-Unisim-Transformation/td-p/509743
01-22-2018 07:24 AM
I am referring xapp524 reference design where IBUFGDS is used in the VHDL code in the place of the differential clock pair. But I want Verilog code. So I am rewriting the VHDL code into Verilog code the meantime I searched in the tool template tab where it is not found. This is my problem. So what to do?
01-22-2018 10:04 AM
Why not just use the regular IBUFDS as it is used in the XAPP524 diagrams for the design clocking structure? Just make sure the rest of the design in local. Or if you have to have the clock be global just append a BUFG to the IBUFDS. Vivado infers IBUFGDS and IBUFDS as the same to reduce complexity. To make the signal a global clock is to use a BUFG on the input clock line.
01-22-2018 12:23 PM
As @vemulad points out.
IBUFGDS is a construct that implies a direct connection from the Clock Capable pin to the clocking network.
Perhaps it was needed in the past to guide the tools but the DRC capabilities in Vivado are able to determine valid clock capable pins.
In this case you can just use an IBUFDS and lock it to a clock capable IO and this will work.