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Observer jheison.mejia
Observer
2,843 Views
Registered: ‎05-23-2012

IO Issues Kintex7

Hi everyone,

 

Can Kintex7 I/O structure generate bias voltage (1.2V)? if the answer is yes, How?

Can Kintex7 I/Os support CML (Current Mode Logic)?

 

Regards,

 


 


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1 Reply
Xilinx Employee
Xilinx Employee
2,819 Views
Registered: ‎08-02-2007

Re: IO Issues Kintex7

There isn't an off the shelf standard for generating a 1.2v bias.  You have access to DCI or IN_TERM, which with a Vcco of 2.4 could generate 1.2v, but that's limited to Single Ended standard.... which seems not to be what you are looking for

 

-Jon

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