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Observer rahul_0308
Observer
296 Views
Registered: ‎05-08-2018

Impact on clock and data using same constraints in ucf file

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Hi..,

Does it impact same Strength on FPGA pins if I give same IOstandard, drive and slew rate for data pin and clock pin?

In the context of Strength

Is there any difference between clock pin and data pin If I give same drive value and slew rate value?

Both can act as same or is there any variation?

In my application,

Data pin and clock pin are driving out from FPGA.

below i mentioned ucf

NET clock LOC = AA17 | IOSTANDARD ="LVCMOS25" | DRIVE = 24 | SLEW = FAST;

NET data_in LOC = M2| IOSTANDARD ="LVCMOS25" | DRIVE = 24 | SLEW = FAST;

please give reply for this post?

thank you..!

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1 Solution

Accepted Solutions
218 Views
Registered: ‎06-21-2017

Re: Impact on clock and data using same constraints in ucf file

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You can drive the clock from any IO pin.  You should receive the clock on a pin that can be connected to a buffer that can directly drive the FPGA's clock tree.  These are pins with GC as part of their signal name.  While electrically the signals may be the same, a bad clock (noisy, ringing) will cause erors on all of your data lines while a bad data bit will only cause errors on that line, so people generally use more care with the clocks.  You can try things like sending the clock differentially, shielding the clock line and terminating the clock to prevent ringing. 

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5 Replies
278 Views
Registered: ‎06-21-2017

Re: Impact on clock and data using same constraints in ucf file

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Are those pins inputs or outputs?  Drive strength means nothing for inputs.  If they are outputs, there is no reason you couldn't set them both to the same settings.  You should be careful with high drive outputs with FAST slew.  If you have too many of them, you can run into ground bounce.  Look for "simultaneously switching outputs"  in a data sheet or IO User's Guide.

273 Views
Registered: ‎09-17-2018

Re: Impact on clock and data using same constraints in ucf file

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Yes,

Until you model your signal integrity you will not know how drive strength affects the timing of your signals from the outputs.  Once you have your signal integrity simulations from your design's IBIS models along with your extracted pcb, then you will see if stronger or weaker drive affects the timing.  Stronger is not necessarily better.  The rule in signal integrity is to use the weakest, slowest drive that meets requirements to prevent RFI, and ground bounce from simultaenous switching.

l.e.o.

 

Observer rahul_0308
Observer
264 Views
Registered: ‎05-08-2018

Re: Impact on clock and data using same constraints in ucf file

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@bruce_karaffa 

@lowearthorbit 

Thank you for responded.

They are output pins..

Here I am trying to send clock and data from one fpga to another fpga.

I am driving the data and clock signals to fpga out pads.

Actually I meant to ask that Do the data pin and the clock pin act same when we applied same drive and slew rate to both?

I want to know Is there any time delay or functionality wise difference between the data pin and clock pin of fpga.

Both pins can act with same effort or with any variance?

Can I directly place a clock signal on any fpga pin (any bank)?

Or Do I need to put extra effort for clock signals?

 

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Observer rahul_0308
Observer
231 Views
Registered: ‎05-08-2018

Re: Impact on clock and data using same constraints in ucf file

Jump to solution

@lowearthorbit 

Thank you for responded.

They are output pins..

Here I am trying to send clock and data from one fpga to another fpga.

I am driving the data and clock signals to fpga out pads.

Actually I meant to ask that Do the data pin and the clock pin act same when we applied same drive and slew rate to both?

I want to know Is there any time delay or functionality wise difference between the data pin and clock pin of fpga.

Both pins can act with same effort or with any variance?

Can I directly place a clock signal on any fpga pin (any bank)?

Or Do I need to put extra effort for clock signals?

 

0 Kudos
219 Views
Registered: ‎06-21-2017

Re: Impact on clock and data using same constraints in ucf file

Jump to solution

You can drive the clock from any IO pin.  You should receive the clock on a pin that can be connected to a buffer that can directly drive the FPGA's clock tree.  These are pins with GC as part of their signal name.  While electrically the signals may be the same, a bad clock (noisy, ringing) will cause erors on all of your data lines while a bad data bit will only cause errors on that line, so people generally use more care with the clocks.  You can try things like sending the clock differentially, shielding the clock line and terminating the clock to prevent ringing. 

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