02-04-2016 03:11 AM
I've instantiated several "BRAM_SDP_MACRO" in my code to store the needed parameters and data to be read by some componenets. (I can't use the native block memory generator, as the BRAM is used within an independent IP).
As the same entity is instantiated several times, I'd like to use external .mem files (or similar files) to initialize the BRAMs. I've also imported .mif files in the "Design sources" but I don't know how to use them.
I used the INIT_FILE, which is in the generics of this primitive, but it works only in the simulation and not in the real FPGA.
I think that I can use the configuration memory for this purpose and I've tried to find a tutorial or document for that, but I couldn't find any.
Can somebody help me and let me know the steps briefly?
I use Vivado 15.2, VHDL and Zynq-7000
Thanks in advance,
02-04-2016 01:17 PM
02-04-2016 01:22 PM
Thanks for the remark.
In fact, as I've used the primitives of Vivado, the introduced function is already used within the code. The problem is that this function (to my knowledge) works only for the simulation and it does not initialize the block ram.
02-05-2016 01:23 AM
should work for synthesis as well as simulation,
its used by things such as the microblaze and picoblaze to load the new programs into the design at synthesis time.
05-15-2019 04:43 AM - edited 05-15-2019 04:44 AM
Same situation for me,
Behaviour, Post Synthesis, Post Implementation simulation works fine (memory initialized) but bitstream leaves whose memory registers empty (default zero's)
Can someone provide example or etc ? If it's possible at all