11-30-2018 01:12 AM - edited 11-30-2018 01:13 AM
I use FPGA SelectIO as HDMI receiver ,the VCCO of FPGA bank is 3.3V,with 50 ohm pull-up resistors.the FPGA is XC7K325-2FFG900.
The issue is that FPGA can capture 720P60 data correctly,but can't capture 1080P60 data correctly.The eye diagram of 10800P60 data is very bad,while the eye diagram of 720P60 data is much better.The line rate of 1080P60 is 1.48Gbps,and the line rate of 720P60 is 742Mbps.
The eye diagram of 10800P60 is shown as below
The eye diagram of 1080P60 data will be perfect when I removed FPGA from the board,with the 50ohm pull-up resistors leaving on the board.
The eye diagram of 10800P60 without FPGA is shown as below
I measured the eye diagram of HDMI sinal of the Genesys Video EVM,which is shown below
It seems that FPGA causes reflection, I just don't know why.
Anyone could help? Thanks!
11-30-2018 01:29 AM
11-30-2018 07:43 AM - edited 12-02-2018 06:47 AM
Thanks for your reply
Schematic is designed refering to Digilent Genesys-2 Video EVM,on which XC7K325T-2FFG900 and HDMI buffer(TMDS141) are used.
hardware : camera-> cable -> connector on the board->HDMI buffer(TMDS181) ->FPGA(selectIO,3.3V HR bank,TMDS_33 standard)
HDMI lines are DC coupled,I'm also terminating HDMI data and clock lines to 3.3V with 50 ohms right at the FPGA's pins.
TP1(test point 1) locates connector on the board,and the eye diagram of TP1 is good.
TP2(test point 2) locates resistor right at the FPGA pins,and the eye diagram of TP2 is bad.
If the camera data is 720P60,the eye diagram of TP2 is much better
Once I removed HDMI buffer and I connected the input and the corresponding output with short jumper,but the eye diagram of TP2 is still bad.
I am totally confused because the eye diagram of TP2 will be almost perfect when the FPGA is removed from the board,with 50 ohm resistor leaving on the board.
It seems that FPGA has some internal termnation ,I guess.While ug471 says:the attribute of "IN_TERM" is "NONE" by default,and it's not supported in TMDS_33 standard.
12-02-2018 06:23 AM - edited 12-02-2018 06:24 AM
In ds182,I find that the throughout of the "DDR LVDS receiver" in HR bank is 1250Mb/s,while the line rate of 1080p60 data is 1.48Gbps,that is much bigger than FPGA SelectIO's max throughput.
Maybe Kintex7 SelectIO is not suitable for 1080p60 HDMI,and the internal structure of SelectIO will cause some reflection when the 1080p60 data come in,am'I right?
12-02-2018 03:20 PM
The max data rate of the IO is typically bounded by the clocking in the IO bank.
Either way you can't achieve these data rates as per the data sheet spec
12-03-2018 07:55 PM
HDMI Clock from Camera is connected to the same bank as the data line,MRCC pins.The frequency of HDMI clock is 148.5Mbps when the resolution is 1080p60.
I'm not sure what is the actual data rates that can be achieved, smaller than 1250Mbps?
12-03-2018 08:19 PM
When you input 148.5MHz via HDMI from camera, actual data rate is 148.5MHz * 10 (Because of HDMI uses 8b10b mechanism.) = 1485Mbps.
Also, I guess, it might be able to receive LVDS IO on 1.8V or 2.5V with AC coupling.
But I'm not sure.
I suggest doing SI simulation first.
12-03-2018 10:08 PM
I also think the LVDS IO can be used to receive HDMI lines with AC coupled,as long as the max data rate of SelectIO is satisfied.
AC coupled can't be achieved on my board so far.I want to find the reason why the issue remains.
12-03-2018 11:13 PM
Do you need to consider compatibility ?
If no, I suggest remove TMDS buffer and using pseudo TMDS which prepares 1.8 or 2.5 LVDS IO with AC coupling.
However, I'm not sure it will be fine or not.
12-03-2018 11:42 PM
I don't need to consider compatibility.
It's hard to palce the AC capacitors and the resistors because the pad of the TMDS buffer is too small.I will try to make it.
I'm also not sure if the 1.8V LVDS or 2.5V LVDS standard is available when the VCCO of the HR bank is 3.3V.