07-05-2013 03:53 AM
I am a new FPGA user, trying to find my way around Kintex-7 480T.
1) I would be using Master BPI configuration mode, for which Spansion S29GL-P or S29GL-S would be employed.
Is there any other advantage of using BPI over SPI other than speed? Are there any drawbacks of using the same?
2) What is the part number of Xilinx connector & cable to be used for indirect programming of the PROM?
3) From what i gather from the configuration document, i would be be requiring the following to be placed on PCB :
b-> Xilinx connector for indirect programming
c-> power & clock sources
d->JTAG connector (Is it different from (b)? )
Is there any other component that needs to be placed?
07-05-2013 10:52 AM - edited 07-05-2013 10:54 AM
BPI's advantage is speed as you have noted. It's drawback is only that it uses up more
pins of the FPGA. However when you look at an FPGA of the density you're using and
figure out how long it would take to use a serial SPI for configuration (even at 4-bits wide)
you might decide that the speed increase is worth it. There are some designs that simply
have no other way to configure because the system requires startup in a fixed amount of time.
The connector for indirect programming is the JTAG connector. The standard connector is
a 2mm shrouded pin header which fits the 1mm-pitch ribbon cable of the USB JTAG programmer.
Our boards use a surface-mounted version, Molex part number 87832-1420.
07-08-2013 02:11 AM
1) This cable (http://www.xilinx.com/products/devkits/HW-USB-II-G.htm) that can be used with 87832-1420 ?
2) If i configure in Master BPI mode, once configuration process ends, the same connector can be used for JTAG debugging purposes & for burning code into FPGA by changing the MODE or is it that, by default, the debugging/code dumping by JTAG can be performed without changing the mode?
3) My setup is in the following manner: I would be using 2 Kintex-7 chips on one board, with one flash per FPGA. None is Master or Slave. They need to be configured simultaneously. is it a good option to buffer the JTAG signals so that only one connector be used?
07-08-2013 07:05 AM
1) Yes that's the correct cable. In this image you can see the ribbon cable at the bottom
that fits the Molex connector. I usually mount the connector near a board edge with the center
key slot facing away from the edge of the board. This allows the cable to plug in without
2) Yes that's right. However you don't need to change the MODE pins. JTAG can always be
used regardless of MODE settings.
3) You can use a single JTAG connector and chain the two FPGA's even if you don't chain
the flash configuration. I don't think you will need to add buffers to the JTAG for just two
devices, but follow the recommendations of the configuration user guide to be sure you
have good signal integrity, especially on the JTAG TCK signal. Remember that these
are very fast circuits, and they don't have hysteresis on the JTAG inputs. So it's important
to have a clean clock transition without reflections that cross into the threshold region.
You should double check that Impact supports indirect BPI programming for the flash
device you have selected. Getting this wrong could be costly if you have to add another
connector or program the flash off-board.
07-09-2013 09:11 PM
Yes will keep that in mind.
1) I would be using 7 pin berkstik (Molex part no.:0022284074) for proto purpose instead . Could you tell the diameter of the Flying wire so that we can ensure that it can be used?
2) The Indirect programming of Kintex-7 family BPI PROM follows the same procedure as the "Indirect Programming of BPI PROMs with Virtex®-5 FPGAs (XAPP973)", isn;t it?
3) Same code needs to be burnt into both FPGA. In this case, programming both the FPGA through a single Flash (same .mcs file) can be done, right? (i would not be chaining the FPGA's as that would create dependency of one FPGA on another) Please have a look at the image attached for the arrangement i ahve in mind.
07-10-2013 08:25 AM
1) I'm not sure of the exact wire diameters, but they are made to fit a standard 0.100" spaced
.025" square post header. The individual leads would also fit some 2mm spaced headers,
but when you try to place two of them on adjacent pins there will be interference, so I would
suggest using the 0.1" pin spacing for the flying leads.
2) I believe this is correct, but again I'd make sure before designing the board. At least open
up the latest version of Impact and try to create a project with one K7 device and an attached
BPI PROM and make sure that the one you're using shows up in the pull-down list. You might
need to create a simple project and build .bit and .mcs files in order to get through the
Impact screens, but you should be able to set it up without hardware (or even a cable).
3) Again I'd make sure that this configuration is shown in the 7-series configuration user
guide, although it seems like it could work if one FPGA is in BPI master mode and the other
is in BPI slave mode. Also note that if either or both FPGA's need to use the BPI flash
for other storage after they are configured, you may have contention issues if you try
to do indirect BPI programming through one FPGA while the other FPGA is running.
In general, I'd stick with a known usable configuration as shown in the user guide.
08-08-2013 05:51 AM
Can you suggest the heat sink for XC7K420T?
We estimated around 15W using XPE software.
You might want to start a new thread for this topic. There are a lot of considerations that go into
choosing a heatsink. For example, how much head room do you have? How much air flow?
How much board space can you add around the FPGA for mounting the heatsink? Is this
going into an enclosure like a PC with room between boards but little airflow, or will it be in
some other enclosure, perhaps with the ability to use the enclosure case itself as a heat sink?