09-29-2018 02:19 AM
Why bank 16 is not available in MIG configurator?
It have VREF pins, DSQ pins, so it look like a normal bank possible to use in DDR interface (except a lower count of pins).
But it is not available in MIG, even to assign ODT or RESET signals. I don't see information about it in any document.
09-29-2018 02:45 AM
09-29-2018 02:51 AM - edited 09-29-2018 02:58 AM
Not supported by MIG?
I quess that FPGA supports this, becouse it will be useless to have VREF and DQS on bank 16 if this functinality may be nonusable.
I don't see information about "suporting" when i select "New Design". There I see that MIG automatically assign signals to banks 33 and 34. And all of banks 13, 14, 14 and 16 are unavailable. There are no information about difference between bank 16 and banks 13/14/15. Simply all of 13...16 banks all unavailable.
09-29-2018 06:43 AM
I’m not familiar with using MIG/MIS. However, I note from comments near Fig 1-11 in UG475 that bank 16 is only partially bonded out for FBG484 package of XC7K70T. Again in UG475, Fig 3-99 shows that FBG484 package is missing the Memory Byte Group-0 pins that are available in the larger FBG676 package (see Fig 3-102). -maybe some help to you?
09-29-2018 10:16 AM
Partial bonding = lower count of pins. I know about it.
But it not explain why bank 16 is excluded* from using in DDR interface.
Form example, when I choose "New Design", MIG autmatically assign pins to banks 33 and 34.
D0...D15 and DQS pins to one bank, A0..A14 and control pins to second bank.
Usage of pins on both banks is smaller than count of pins in bank 16. So count of pins is not an issue. MIG could assign pins to banks 15 and 16 and count of pins will be sufficient. So there must be another reason.
*or maybe not, maybe it is a bug in MIG configutator.
10-03-2018 10:47 AM
Partially bonded IO banks are disabled in the MIG "New Design" pin/bank selection mode. You will need to use the "Fixed Pin Out" mode for this BUT MIG may incorrectly calculate some of the pinout parameters leading to certain implementation errors. Because of this YOU need to manually verify the pinout parameters. You will need to use a combination of the ASCII pinout and vivado device view to see which pins are not bonded out within an incomplete byte group.
Take your case for example, Bank 16 of the Kintex 70T device in the fbg484 package has pin 0 missing in byte groups T2 & T3, while T0 only has pin 0 bounded out but none of the other 11 pins. You will likely run into implementation errors and discover that the PHY_0_BITLANES, BANK_MAP, and CKE_MAP parameters may be calculated incorrectly due to the missing pins in this bank. It is advised to check all pinout parameters related to the partial I/O bank.