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Visitor leopold2019
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Registered: ‎07-04-2019

Kintex-7 output differential clock is weak

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Hi,

I use FPGA output a pair differential clock, The output differential clock is from a single end one that is one of output clock of MMCM.

I found that the frequary of output differential clock is correct,but the swing is small.

the IO standard of output clock is DIFF_HSTL_II_18.

IMG_20190720_082251.jpg

What causes this problem?

Regards.

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145 Views
Registered: ‎01-22-2015

Re: Kintex-7 output differential clock is weak

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j@leopold2019 

You will find electrical characteristics for DIFF_HSTL_II_18 in the datasheet, DS182, for the Kintex-7.

https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

 

The DIFF_HSTL_II_18 standard is available in both HP and HR banks of the Kintex-7 and outputs are current limited to 16mA, per Table 11 in DS182.

Please read UG471 about proper termination for DIFF_HSTL_II_18 since improper termination can reduce output swing.  Also, check input impedance setting for your oscilloscope since it can cause improper termination for DIFF_HSTL_II_18.

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Mark

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146 Views
Registered: ‎01-22-2015

Re: Kintex-7 output differential clock is weak

Jump to solution

j@leopold2019 

You will find electrical characteristics for DIFF_HSTL_II_18 in the datasheet, DS182, for the Kintex-7.

https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

 

The DIFF_HSTL_II_18 standard is available in both HP and HR banks of the Kintex-7 and outputs are current limited to 16mA, per Table 11 in DS182.

Please read UG471 about proper termination for DIFF_HSTL_II_18 since improper termination can reduce output swing.  Also, check input impedance setting for your oscilloscope since it can cause improper termination for DIFF_HSTL_II_18.

https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

Mark