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Explorer
Explorer
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Registered: ‎10-27-2013

LVDS_25 & 1.8V LVDS input to Artix HR bank

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I am using ARTIX FPGA XC7A200T. I am interfacing a 1.8V LVDS ADC to FPGA's HR I/O bank which is powered at 2.5V.

I have routed to LVDS_25 terminals of FPGA as input terminals.

I intend to use FPGAs internal differential termination for LVDS. Is this possible or allowed?? I have not provided external termination.

What are the limitation of this approch??

If i want to make use of differential termination what is the approch?? Do i need to route all LVDS to HP I/Os . Please elaborate.

 

 

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Scholar u4223374
Scholar
104 Views
Registered: ‎04-26-2015

Re: LVDS_25 & 1.8V LVDS input to Artix HR bank

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Correct on all counts.

There are really two issues here:

- Can you use the internal LVDS termination on a HR bank powered from 2.5V? The answer is an unequivocal "yes". This is absolutely, 100% supported.

- Can you plug 1.8V LVDS into a 2.5V LVDS bank? This is not 100% guaranteed, but it's very close. Because LVDS doesn't swing rail-to-rail (unlike, for example, LVCMOS) the supply voltage doesn't matter much - and so generally you can plug any LVDS output into any LVDS input, regardless of supply voltages. If you check the datasheets it'll be clear. In the Kintex 7 one you need Table 12 on Page 11. As long as the ADC meets V_IDIFF and V_ICM requirements (which are very wide, and should be met by pretty much any LVDS transmitter) then you're safe.

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Scholar u4223374
Scholar
150 Views
Registered: ‎04-26-2015

Re: LVDS_25 & 1.8V LVDS input to Artix HR bank

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That all sounds like it should work.

 

You just need to ensure that the 1.8V ADC voltage levels are appropriate for the 2.5V LVDS input, but they generally are fine.

 

The only "limitation" of this approach (compared to the HP banks) is that the HR banks aren't as fast - but they're fast enough for most purposes.

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Explorer
Explorer
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Registered: ‎10-27-2013

Re: LVDS_25 & 1.8V LVDS input to Artix HR bank

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In the link given below

https://www.xilinx.com/support/answers/43989.html

If bank voltage is LVDS_25 is set to VCCO = 2.5V then I will  be able to use internal differential terminal of LVDS_25 even if I connect 1.8V LVDS.

So as you said other than performance degradation at high frequency there is no other concern.

 

FPGA_LVDS.jpg
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Scholar u4223374
Scholar
105 Views
Registered: ‎04-26-2015

Re: LVDS_25 & 1.8V LVDS input to Artix HR bank

Jump to solution

Correct on all counts.

There are really two issues here:

- Can you use the internal LVDS termination on a HR bank powered from 2.5V? The answer is an unequivocal "yes". This is absolutely, 100% supported.

- Can you plug 1.8V LVDS into a 2.5V LVDS bank? This is not 100% guaranteed, but it's very close. Because LVDS doesn't swing rail-to-rail (unlike, for example, LVCMOS) the supply voltage doesn't matter much - and so generally you can plug any LVDS output into any LVDS input, regardless of supply voltages. If you check the datasheets it'll be clear. In the Kintex 7 one you need Table 12 on Page 11. As long as the ADC meets V_IDIFF and V_ICM requirements (which are very wide, and should be met by pretty much any LVDS transmitter) then you're safe.