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Observer starting
Observer
208 Views
Registered: ‎08-10-2018

LVDS with pullup to 3.3 V

Hello,

i recently found out that some of the LVDS buffers used in a design can enter a state where they act like a ~5 µA / 660 kOhm pullup to 3.3 V on the datalines (input as well as output).
These inputs or outputs are connected to 7 series FPGAs with their IO banks running at 1.8 or 2.5 V.
Configuration is set to LVDS or LVDS_25 and on chip termination is activated.
Is this something to be concerned about?
Our prototypes seem to be working fine and as 5 µA are quite low compared to what the internal diodes can take i suspect this causes no further damage (even considering scenarios like backpowering if one device has lost power).

Thanks in Advance


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9 Replies
Scholar watari
Scholar
204 Views
Registered: ‎06-16-2013

Re: LVDS with pullup to 3.3 V

Hi @starting 

 

It's to prevent input floating issue.

Would you refer the following LVDS owner's manual, if you want to know more detail ?

 

http://www.ti.com/lit/ug/snla187/snla187.pdf

 

Best regards,

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183 Views
Registered: ‎01-22-2015

Re: LVDS with pullup to 3.3 V

@starting 

    ... 660 kOhm pullup to 3.3 V ...  Is this something to be concerned about?
No.  -both from an LVDS performance viewpoint and from an FPGA damage viewpoint.

You seem most worried about the FPGA damage viewpoint.  Note from table of "Recommended Operating Conditions" in the datasheet (eg. DS182 for Kintex-7) that max current through any FPGA pin (powered or unpowered) should not exceed ~10mA.  So, when FPGA pin is unpowered (ie. at 0V) it will draw only 3.3/660000=0.005mA from "660 kOhm pullup to 3.3 V".

Mark

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Explorer
Explorer
174 Views
Registered: ‎09-17-2018

Re: LVDS with pullup to 3.3 V

What device family?

What is the bank's Vcco?

l.e.o.

 

Observer starting
Observer
161 Views
Registered: ‎08-10-2018

Re: LVDS with pullup to 3.3 V

Thank you very much for the answers.
There are different devices in the system like Artix and Zynq 7020, but they are all 7-series. Some banks are powered by 2.5V and others 1.8 V.
The 3.3 V can be measured at the inputs as well as the outputs of a LVDS buffer which isn't connected to another device.


@watari wrote:

Hi @starting 

It's to prevent input floating issue.

Would you refer the following LVDS owner's manual, if you want to know more detail ?

http://www.ti.com/lit/ug/snla187/snla187.pdf

Best regards,


I searched the document for "float" and "pull", but couldn't find something about preventing issues with floating inputs.
Could you give me a hint where to find more information about this mechanism?

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147 Views
Registered: ‎01-22-2015

Re: LVDS with pullup to 3.3 V

@starting 

I am sorry.  My previous answer to you is incomplete and possibly incorrect - because I only considered the over-current restrictions of the FPGA pins. 

@lowearthorbit  has kindly reminded us that we must also consider the over-voltage restrictions of the FPGA pins.  I hope he will comment further.

Perhaps something as simple as a 10K-ohm pull-down resistor on each LVDS line (currently pulled up thru 660K-ohm to 3.3V) would prevent any over-voltage problems at the FPGA pins (and not cause other problems)?

Mark

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Scholar watari
Scholar
144 Views
Registered: ‎06-16-2013

Re: LVDS with pullup to 3.3 V

Hi @starting 

 

Would you read "4.6 Failsafe" section and refer the following document, too ?

 

http://www.ti.com/lit/an/snla051b/snla051b.pdf

 

Best regards,

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Explorer
Explorer
114 Views
Registered: ‎09-17-2018

Re: LVDS with pullup to 3.3 V

Ok,

(commenting further...)

Still do not know which device, what Vcco of bank is; however, the damage will occur if values in Table 1 of the data sheet are exceeded.  A signal integrity simulation using IBIS models is required to see the actual voltages (currents) at the pins.

l.e.o.

 

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Observer starting
Observer
96 Views
Registered: ‎08-10-2018

Re: LVDS with pullup to 3.3 V

Thank you very much.

@lowearthorbit There are different 7-series devices with bank voltages of 1.8 or 2.5 V.
7 of the 8 LVDS channels go from a Zynq 7020 through the LVDS buffers (FIN1104, https://www.onsemi.com/pub/Collateral/FIN1104-D.pdf) into modules with a Kintex or Artix FPGA. But there is also one channel for the opposite direction (Kintex -> Buffer -> Zynq).
The FPGAs have LVDS, DIFF_TERM=True and 1.8 V bank voltage on HP banks.
The Zynq uses LVDS_25, DIFF_TERM=True and 2.5 V bank voltage on a HR bank.

Reading the linked documents about LVDS and measuring a bit more i think i start to see the reason for the behaviour of the buffer.
As said by @watari, pull-ups are used to detect/handle the failsafe conditions.
The inputs have weak pull-ups (4,5 µA) on the positive input and pull-downs (1,5 µA, not very accurate multimeter) on the negative input.
Without this an undriven and unterminated input ("open input failsafe", TI application note: http://www.ti.com/lit/an/snla051b/snla051b.pdf) would be very sensitive to noise. Thanks to these hidden, internal resistors the outputs of the buffer reach normal LVDS levels with a constant '1' as indicated in the buffer datasheet .

An undriven but terminated input ("terminated failsafe", TI application note) results in both inputs weakly pulled to VCC=3.3V. This doesn't fit to the aforementioned weak resistors. Even worse, the outputs also reach 3.3 V. I will have to take the time and measure more thoroughly.

markg@prosensing.com  and @lowearthorbit  the table 2, "recommended conditions" and table 1 "absolute maximum ratings" of the 7 series FPGA datasheet (https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf) show a maximum input voltage of VCC + 0.2 and VCC + 0.55 V.
This seems to be caused by the ESD protection diodes, which start conducting for higher voltage levels. Each of these diodes can conduct 10 mA and the bank should be driven by less than 200 mA in total.
In my case we are far away from these limits as the weak pull-ups of the buffers to 3.3 V will introduce 7x4.5 ~ 35 µA. But i'm not sure if there is another effect that I'm missing or misunderstanding entirely.

I guess it is easier to implement external "failsafe bias" (TI application note) and add some resistors to the 100 ohm input termination .
This would avoid the 3.3 V at the outputs as well as the inputs, but takes more space and impairs the signal performance.

Any ideas and experiences?

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87 Views
Registered: ‎01-22-2015

Re: LVDS with pullup to 3.3 V

@starting 

With your VCCO=1.8V (or 2.5V), the “660K pullup to 3.3V” could (strictly speaking) violate the Absolute Maximum Ratings (see Table 1 of DS182) for VIN of (VCCO+0.55) – if no current were being drawn through the 660K pullup resistor.  There are some types of electrical failure (eg. punch-through) that can occur at over-voltage conditions and at very low current.  I don’t know if this failure mechanism can happen at the FPGA pins, but without further guidance, we must assume that it can.

As lowearthorbit says, you can use IBIS models for the FPGA pins and third-party software to study whether the “660K pullup to 3.3V” will actually apply a voltage greater that (VCCO+0.55) to the FPGA pin – or whether leakage currents through the 660K pullup will occur and drop the 3.3V to a value that is less than (VCCO+0.55).  As I suggested earlier, you could ensure that a leakage current is present by placing a 10K-ohm pulldown resistor on each of your LVDS lines.  These pulldowns would ensure that the FPGA pins (and LVDS lines) never see the 3.3V or anything above (VCCO+0.55).

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