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Visitor marcovaldo
Visitor
224 Views
Registered: ‎11-17-2018

Latch Problems

the problem that i have is caused by conc1,conc2,conc3,conc4 that are bytes' vectors, i don't know why each byte can generate a latch even if i have initiliazed them and each if , or case statements, have something to do for all options.
 
these are the warnings:
 
WARNING:HDLCompiler:92 - "/home/ise/XilinxVirtualMachineHost/Xilinx/Tastierino4/tastierino4.vhd" Line 157: sbagliato should be on the sensitivity list of the process
WARNING:HDLCompiler:92 - "/home/ise/XilinxVirtualMachineHost/Xilinx/Tastierino4/tastierino4.vhd" Line 158: conc1 should be on the sensitivity list of the process
WARNING:Xst:737 - Found 1-bit latch for signal <conc1<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc1<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc1<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc1<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc1<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc1<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc1<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc2<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc2<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc2<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc2<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc2<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc2<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc2<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc3<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc3<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc3<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst
 
:737 - Found 1-bit latch for signal <conc3<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc3<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc3<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc3<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc4<7>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc4<6>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc4<5>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc4<4>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc4<3>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc4<2>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
WARNING:Xst:737 - Found 1-bit latch for signal <conc4<1>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
 
these are code's lines:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

 

entity tastierino4 is
Port ( col : in STD_LOGIC_VECTOR (3 downto 1);
row : in STD_LOGIC_VECTOR (4 downto 1);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
conc : out STD_LOGIC_VECTOR (28 downto 1));
end tastierino4;

architecture Behavioral of tastierino4 is

type state is (s0,s1,s2,s3,se1,se2,se3,s4,se4);
signal curr_state, next_state: state;
signal conc1,conc2,conc3,conc4: STD_LOGIC_VECTOR (7 downto 1):="0000000";
signal sbagliato: std_logic;

begin

current_state_register: process(clk)
begin
if rising_edge(clk) then
if rst='1' then
curr_state<=s0;
else
curr_state<=next_state;
end if;
end if;
end process;

next_state_register:process(col,row,curr_state)
begin

case curr_state is
when s0=>if((col="011" or col="101" or col="110" or col="111") or (row="0011" or row="0101" or row="0110" or row="0111" or row="1001" or row="1010" or row="1011" or row="1100" or row="1101" or row="1110" or row="1111")) then
next_state<=se1; --errore
elsif (( col="001" or col="010" or col="100") and (row="0001" or row="0010" or row="0100" or row="1000")) then
conc1<=col & row;
next_state<=s1; --valido
elsif(col="000" and row="0000")then
next_state<=s0;
else next_state<=s0;
end if;
when s1=>if((col="011" or col="101" or col="110" or col="111") or (row="0011" or row="0101" or row="0110" or row="0111" or row="1001" or row="1010" or row="1011" or row="1100" or row="1101" or row="1110" or row="1111")) then
next_state<=se2; --errore
elsif (( col="001" or col="010" or col="100") and (row="0001" or row="0010" or row="0100" or row="1000")) then
conc2<=col & row;
next_state<=s2; --valido
elsif(col="000" and row="0000")then
next_state<=s1;
else next_state<=s1;
end if;
when s2=>if((col="011" or col="101" or col="110" or col="111") or (row="0011" or row="0101" or row="0110" or row="0111" or row="1001" or row="1010" or row="1011" or row="1100" or row="1101" or row="1110" or row="1111")) then
next_state<=se3; --errore
elsif (( col="001" or col="010" or col="100") and (row="0001" or row="0010" or row="0100" or row="1000")) then
conc3<=col & row;
next_state<=s3; --valido
elsif(col="000" and row="0000")then
next_state<=s2;
else next_state<=s2;
end if;
when s3=>if((col="011" or col="101" or col="110" or col="111") or (row="0011" or row="0101" or row="0110" or row="0111" or row="1001" or row="1010" or row="1011" or row="1100" or row="1101" or row="1110" or row="1111")) then
next_state<=se4; --errore
elsif (( col="001" or col="010" or col="100") and (row="0001" or row="0010" or row="0100" or row="1000")) then
conc4<=col & row;
next_state<=s4; --valido
elsif(col="000" and row="0000")then
next_state<=s3;
else next_state<=s3;
end if;
when se1=>if(col="000" and row="0000") then --/0
next_state<=se1;
elsif(col="---" and row="----")then --X
next_state<=se2;
else next_state<=se1;
end if;
when se2=>if(col="000" and row="0000") then --/0
next_state<=se2;
elsif(col="---" and row="----")then --X
next_state<=se3;
else next_state<=se2;
end if;
when se3=>if(col="000" and row="0000") then --/0
next_state<=se3;
elsif(col="---" and row="----")then --X
next_state<=se4;
else next_state<=se3;
end if;
when s4=>if((col="011" or col="101" or col="110" or col="111") or (row="0011" or row="0101" or row="0110" or row="0111" or row="1001" or row="1010" or row="1011" or row="1100" or row="1101" or row="1110" or row="1111")) then
next_state<=se1; --errore
elsif (( col="001" or col="010" or col="100") and (row="0001" or row="0010" or row="0100" or row="1000")) then
next_state<=s1; --valido
elsif(col="000" and row="0000")then
next_state<=s4;
else next_state<=s4;
end if;
when se4=>if((col="011" or col="101" or col="110" or col="111") or (row="0011" or row="0101" or row="0110" or row="0111" or row="1001" or row="1010" or row="1011" or row="1100" or row="1101" or row="1110" or row="1111")) then
next_state<=se1; --errore
elsif (( col="001" or col="010" or col="100") and (row="0001" or row="0010" or row="0100" or row="1000")) then
next_state<=s1; --valido
elsif(col="000" and row="0000")then
next_state<=se4;
else next_state<=se4;
end if;
when others=>if(col="---" and row="----") then
next_state<=s0;
else
next_state<=s0;
end if;
end case;
end process;

output_function:process(curr_state)
begin
case curr_state is
when s0=>sbagliato<='0';
when s1=>sbagliato<='0';
when s2=>sbagliato<='0';
when s3=>sbagliato<='0';
when s4=>sbagliato<='1';
when se1=>sbagliato<='0';
when se2=>sbagliato<='0';
when se3=>sbagliato<='0';
when se4=>sbagliato<='0';
when others=> sbagliato<='0';
end case;

if sbagliato='1' then
conc<=conc1 & conc2 & conc3 & conc4;
else
conc<=(others=>'1');
end if;
end process;


end Behavioral;

 

0 Kudos
2 Replies
212 Views
Registered: ‎06-21-2017

Re: Latch Problems

But you don't define con1, conc2, conc3 or conc4 for all conditions, for instance you assign conc1 in state s0 but do not assign any values to conc2, conc3 or conc4.  These signals will create latches since they must hold their values in state s0. 

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Scholar u4223374
Scholar
208 Views
Registered: ‎04-26-2015

Re: Latch Problems

@marcovaldo A latch is formed when you've got a non-clocked process that does not define all of its outputs as a combination of its inputs.

 

In your case, suppose that col = 111 and curr_state = s0. What is the value of conc1 going to be? In this scenario you do not define the output - you're asking the synthesis tool to hold the same value. Since this process is not driven by a clock, it can't use a flip-flop - so it has to use a latch instead.

 

The solution is to either (a) move this to a clocked piece of logic so that the synthesis tool can use a flip-flop, or (b) define what every output must be for every possible input combination.

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