03-01-2018 08:02 AM
I need to design a component and choose on which FPGA i will implement it.
One module of the FPGA will be synchronous of a signal TXCLK that is generated by an external component the LM98640 and the frequency of TXCLK is about 640 MHz.
I've read the datasheets but i'm not sure which parameter i should check to be sure that the FPGA can work with signals as fast a 640 Mhz
I'm aware that the way i design it will affect the maximum operating frequency, but i'm looking for the values for each FPGA in case the design is really simple of maximum frequency.
I'm confused between Digital Frequency Synthesizer (DFS) or Delay-Locked Loop (DLL) or GTP transceiver clock ?
03-01-2018 08:22 AM
Drives what, exactly?
If it drives an internal global clock buffer, BUFG, the datasheet will show the Fmax for that. There will be Fmax for various blocks, see ds925, table 83 (DSP48). For BUFG, see table 84.
If it is a reference clock, for the transceivers, it will not be the rate of the data bits (25 Gb/s is not 25 GHz ref clock, it is much lower, and multiplied up to 25 GHz).
Optimal design in FPGA devices goes with a slower clock, and wider words of bits. Not unusual to operate on 256 bits in one clock cycle at 300 MHz, so bandwidth is 300E6 * 256 b/s, or 76.8 Gbs.
The MMCM (PLL) in 7 series and later devices also has a Fmax in the datasheet (DCM last used in 6 series, replaced by MMCM and PLL in CMT).
03-01-2018 08:31 AM
Well i'm going to use TXCLK for a shift register.
On each transitions of TXCLK (rising and falling edge) i am going to shift the value of a 14 bits register.
I will write a VHDL code with a process synchronous to the signal TXCLK
03-01-2018 08:39 AM
What device family are you targeting? You will notice that newer families run faster, and older families may need the fastest speed grade (or may not be fast enough).
Typically, one would use 1/2 the clock rate, and use DDR IO, and operate on two bits every clock, not one (dual data rate design). Both the rising, and falling edges of the 1/2 rate clock are used, allowing for a less expensive device, lower speed grade.
03-01-2018 08:53 AM
I don't know which family i'm targetting, i have been checking the datasheet and sometimes there is a reference to BUFG, sometimes to BUFGCTRL and othertimes to BUFGMUX, is it basically the same?
03-01-2018 08:55 AM
The base cell is the BUFGMUX/CE, in its simplest form, with no mux, no ce, it is a BUFG.
03-06-2018 02:06 AM
I want to deserialize data out of a LM98640 which data rate is configurable from 40 Mbps to 640 Mbps, i will use an FPGA of series 7. I will use the ISERDESE2 to achieve the deserialisation
I assume if i use ISERDESE2 that i should look at another frequency parameter, not only the BUFG?
03-06-2018 07:24 AM
For that range of frequencies, it is likely your design will have no issues meeting timing until the rate gets beyond 300-400 MHz, where using DDR would make timing easier to meet (design using both rising and falling edges of clock to transfer data).
As I am not familiar with the LM device, I really cannot help you there.
03-06-2018 07:48 AM