06-12-2019 02:28 PM
I see in the Kintex-7 datasheet under "recommended operating conditions" that any pin can have a mamximum input current of 10mA, and each bank should be limited to 200mA total.
Can I asssume the maximum sink current for every IO is 10mA, or am I looking at the wrong table?
Thanks in advance!
06-12-2019 02:57 PM
You have the correct document, table, and specifications.
However, if a bank has more than 20 IO then sinking 10mA into every IO of the bank will exceed the 200mA-per-bank spec.
You can see how IO are grouped into banks by looking at the package drawings for your FPGA in Xilinx document UG475.
06-12-2019 03:01 PM
Depending on the setting for the pin IO standard,
You get a minimum current (for example 24 mA LVCMOS) will sink, or source 24 mA, minimum.
You must stay within bank simultaneous switching requirements for signal integrity. The tools will report any issues (too many strong ouputs all switching on the same clock edge).
06-13-2019 12:37 PM
10mA per IO /200mA per bank refers to the case where you have activated the clamp and are sinking current into it.
"You get a minimum current (for example 24 mA LVCMOS) will sink, or source 24 mA, minimum."
I'm not sure this is correct. 24mA would indicate the size of the load you can drive and still be sure of the output logic levels.
I think the bottom line is that the IO will source and sink a lot of current depending on its on resistance and the load it is connected to. Whether you get a usable logic signal is a different matter.