12-14-2017 01:49 AM
Dear all, (I opened a new thread on this location, the old one was misplaced)
my question refers to OSERDESE Reset handling ...
The quesion is simple: "How to properly reset an OSERDES core?"
PG070, UG471 and xapp594 confuse me a little since they all say different things, leave things out or don't refer to the signal names as they appear in the SelectIO Interface Wizard.
1) every guide tells the user to send a "reset" to the OSERDES. What is meant here? io_reset or clk_reset or both? I assume that the guides refer to the io_reset - but what about the clock reset? Don't I necessarily need to reset the clock circuitry within the OSERDES?
2) XAPP594 describes that the "enable input" should be kept deasserted for "a number" of clock cycles. What is meant with "enable input" and what is "a number"? Does the number have to fulfil certain restrictions? In addion to that, my SelectIO Wizard shows no "enable input" or OCE. There's only a "clock_enable" which can be be activated or not ....
3) It would be nice to have a timing diagram for resetting the OSERDESE properly. I think that the reset method for the OSERDES is independent from the application ... Maybe some can supply with a timing diagram that worked for them?
Some additional information about my application:
The OSERDES is going to drive the parallel input of a DAC. So I could almost use xapp594 as a recipe which was very nice up to a certain extend. If I implement my design and test It, I experience a somewhat weird behaviour everytime I reset the FPGA. most of the time I see two different phase states of my DAC output signal. I've analysed the parallel port between FPGA and DAC with high speed diff. probes and I could verify that the Data samples always have one out of two distinct phases relative to the DAC clock after each reset. I Use two OSERDES to drive Port A and B of the DAC. I use a third OSERDES with a constant data input (0101) as the clock generator to the DAC. DAC is AD9129. All the logic is clocked with CLK_DIV (234MHz). Resets are synced to this clock. OSERDES CLK is 468 MHz.
Any help or suggestion is very appreciated :) Thanks a lot
P.S.: Im Using Vivado 2017.3 and my design is going to be used on a KINTEX-7 FPGA on a custom built PCB.
12-19-2017 12:50 AM
The Reset sequence I would use is:
First if you have a clock manager is deassert the clock manager reset wait for LOCKED to go high. Then the suggested order is to deassert IDELAYCTRL reset, wait for IDELAYCTRL RDY to go high, then you can deassert the IDELAY, ODELAY, ISERDES, and/or OSERDES out of reset. Next enable the ISERDES and OSERDES synchronously with CLKDIV.
- Assume that a MMCM to generate the 200 MHz for the IDELAY_CTRL.
- The MMCMs also generates other clocks in the design.
- Assuming that as in most designs the implemented system reset net has a IGNORE timing constraint.
- Route the system reset only to the MMCM(s) reset input and if necessary to the parts of the design that dont get a clock from one of the MMCM used.
- After releasing the reset, wait until the MMCM shows LOCKED.
o This is something that can be done per MMCM.
o Unless the application uses clocks from different MMCMs, then wait until all MMCM show LOCKED high.
- For the MMCM(s) that deliver clocks to any ISERDES or OSERDES part of the design do then:
o After LOCKED of the MMCM is high take the IDELAY_CTRL components in the design out of reset.
o Wait now until the IDELAY_CTRL shows RDY active.
o Now you can take the IDELAY, ODELAY, ISERDES, and/or OSERDES out of reset.
But keep the ISERDES and OSERDES still disabled!
o Wait for a couple of CLKDIV cycles and the enable the ISERDES and OSERDES.
01-09-2018 02:13 AM
thanks for your input. i will check the list you provided and make sure that i have all the steps implemented.
althought i got the OSERDES in the meantime, i still am confused about the simulation result.
07-21-2018 02:40 PM
This is an excellent answer. Thank you.
I've been using the Processor System Reset IP to get the resets going, but that never produced exactly what the SelectIO Wizard wanted for reset inputs. In particular, the PSR IP doesn't take the idelaycntl_locked signal as an input.
Is there an IP block that handles all the resets correctly for SelectIO blocks that include clock recovery? This seems like a fairly obvious thing that Xilinx would supply, but I haven't found it.