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Observer jheison.mejia
Observer
3,831 Views
Registered: ‎05-23-2012

PCIe x2 Kintex7 Pins

Hi everyone,

 

I have a KC705 Evaluation Platform and I want to test the PCIe x2 comunnication. Could I connect for example in my KC705 the RX1, RX6, TX3, TX5 and the CLK (all pins P and N) in any order to a comunnication x2 with other PCIe x2 connector?

 

Or I need a sequence RX1, RX2, TX1, TX2. Which are the advantages and disavantages using a different sequence?

 

Thanks and regards.

 

Eng. Jheison Mejía

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2 Replies
Xilinx Employee
Xilinx Employee
3,826 Views
Registered: ‎01-03-2008

Re: PCIe x2 Kintex7 Pins

I am confused by your post because PCIe general comes in 1x, 4x and 8x  lane widths.  The 2x lane width is allowed, but not implemented in real world design.

 

The KC705 is a fixed implementation with specific GTX locations to PCIe lane connections.  Your design must conform these locations or it will not work.

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Observer jheison.mejia
Observer
3,823 Views
Registered: ‎05-23-2012

Re: PCIe x2 Kintex7 Pins

Hi mcgett,

 

Thanks for you answer. I can to use in the "7 Series Integrated Block for PCI Express" a Lane Width X2 because I need to connect a DSP 6670 that supports a single bi-directional link interface with a maximum of two lanes width (X2).

 

My question is the KC705 have a PCIE_RXn_P and N with n between 0 and 7. ¿Could I connect the RX0, RX5, TX2 and TX5 with my two DSP lanes TX1, TX2, RX1 and RX2, changing in planahead the respectiblity pins for my FPGA? or I need connect RX0, RX1, TX0 and TX1.

 

Thanks again,

 

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