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Visitor hmeier88
Visitor
413 Views
Registered: ‎07-16-2018

Packaging Issue

Hi!

 

I'm using the Mimas V2 Spartan 6 board and trying to debug the LPDDR.

For example Port mcbx_dram_cke (which is located on G1), I tried it two ways and question is what's the correct one and how can I solve the error?

 

So I created an IP that routes a port from LPDDR wrapper to a LED.

Eg.:

module dpd(
    input CS,
	 output STATUS_LED1
    );

assign STATUS_LED1 = CS;

endmodule

Way 1 (UCF):

Connecting CS from my IP to LOC=G1. 

UCF:

NET "dpd_0_CS_pin"  LOC = "G1" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = SLOW;

NET "dpd_0_STATUS_LED1_pin" LOC=P15;

Ports:

x1.jpg

But it's getting me the following error:

Mapping design into LUTs...
Writing file system_map.ngm...
Running directed packing...
ERROR:Pack:2811 - Directed packing was unable to obey the user design
   constraints (LOC=G1) which requires the combination of the symbols listed
   below to be packed into a single IOB component.

   The directed pack was not possible because: More than one pad symbol.
   The symbols involved are:
   	BUF symbol "dpd_0_CS_pin_IBUF" (Output Signal = dpd_0_CS_pin_IBUF)
   	PAD symbol "dpd_0_CS_pin" (Pad Signal = dpd_0_CS_pin)
   	PAD symbol "mcbx_dram_clk_n" (Pad Signal = mcbx_dram_clk_n)

Way 2 (Ports):

Second Way is connecting it through the EDK port Editor like:

x2.jpg

 

But this way gives me the error:

ERROR:Place:1073 - Placer was unable to create RPM[IOB_RPMs] for the component
   dpd_0_STATUS_LED1_pin of type IOB for the following reason.
   The reason for this issue:
   All of the logic associated with this structure is locked and the relative
   placement of the logic violates the structure. The problem was found between
   the relative placement of IOB dpd_0_STATUS_LED1_pin at site PAD99 and OLOGIC
   LPDDR/LPDDR/mcb_ui_top_0/mcb_raw_wrapper_inst/ioi_cke_0 at site OLOGIC_X0Y53.
ERROR:Place:1073 - Placer was unable to create RPM[IOB_RPMs] for the component
   dpd_0_STATUS_LED1_pin of type IOB for the following reason.
   The reason for this issue:
   All of the logic associated with this structure is locked and the relative
   placement of the logic violates the structure. The problem was found between
   the relative placement of IOB dpd_0_STATUS_LED1_pin at site PAD99 and OLOGIC
   LPDDR/LPDDR/mcb_ui_top_0/mcb_raw_wrapper_inst/ioi_cke_0 at site OLOGIC_X0Y53.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
ERROR:Xflow - Program map returned error code 2. Aborting flow execution...

Or can't I connect mcbx_dram_cke to a LED?

 

Help is really appreciated.

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1 Reply
Xilinx Employee
Xilinx Employee
349 Views
Registered: ‎03-07-2018

Re: Packaging Issue

Hi @hmeier88

 

Did you tried running mentioned design in ISE 14.7 ?

 

Regards,

Bhushan

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Regards,
Bhushan

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