UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor queue1114
Visitor
851 Views
Registered: ‎04-06-2012

Place 30-574 Error.

Jump to solution

Greetings all,

 

I am using a Xilinx KC-705 Dev board. The system clock is differential and routed to AD12 (pos) and AD11 (neg).These are MRCC pins. On the input, I route this to an IBUFDS. The output of which goes several places, including into an MMCM module.

 

I am using Vivado v2017.2 (64-bit). No matter what I do, this error will not go away. Apparently this dev board seems to be using the wrong pins for the SYSCLK.

 

Are there replacement boards with the correct pins? If so, can I replace the one that I have? If not, should I lower the 200MHz clock to a non dedicated route? Although I don't think the fabric can handle 200MHz as non-dedicated.

 

Any suggestions will be greatly appreciated.

 

Thanks in advance - Jim B.

0 Kudos
1 Solution

Accepted Solutions
Scholar jmcclusk
Scholar
1,087 Views
Registered: ‎02-24-2014

Re: Place 30-574 Error.

Jump to solution

ah..  your BUFG is being placed on the wrong half (either top or bottom) of the FPGA.   The solution is to place a LOC constraint on that BUFG so it's in the same half as your input pin.    Open the routed (or placed design) and look at the placement to find a good spot.    Try something like BUFGCTRL_X0Y0

Don't forget to close a thread when possible by accepting a post as a solution.
4 Replies
Scholar jmcclusk
Scholar
842 Views
Registered: ‎02-24-2014

Re: Place 30-574 Error.

Jump to solution

It would help to show the entire error message...  There must be meta data that explains the error.

Don't forget to close a thread when possible by accepting a post as a solution.
0 Kudos
Visitor queue1114
Visitor
838 Views
Registered: ‎04-06-2012

Re: Place 30-574 Error.

Jump to solution

Yes, here it is:

 

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
    < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fmc_hpc_la02_n_IBUF] >

    fmc_hpc_la02_n_IBUF_inst (IBUF.O) is locked to IOB_X0Y211
     and fmc_hpc_la02_n_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

0 Kudos
Scholar jmcclusk
Scholar
1,088 Views
Registered: ‎02-24-2014

Re: Place 30-574 Error.

Jump to solution

ah..  your BUFG is being placed on the wrong half (either top or bottom) of the FPGA.   The solution is to place a LOC constraint on that BUFG so it's in the same half as your input pin.    Open the routed (or placed design) and look at the placement to find a good spot.    Try something like BUFGCTRL_X0Y0

Don't forget to close a thread when possible by accepting a post as a solution.
Highlighted
Visitor queue1114
Visitor
818 Views
Registered: ‎04-06-2012

Re: Place 30-574 Error.

Jump to solution
Thanks - that worked. Surprised the P&R tool didn't know that to begin with.
0 Kudos