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Explorer
Explorer
2,325 Views
Registered: ‎09-02-2009

Pulse width of RESET in XADC module

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Hi experts,

 

Can you tell me the minimum pulse width of RESET input signal for XADC? I can't find it in UG480.

 

Thanks.

Chris

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Explorer
Explorer
3,091 Views
Registered: ‎09-02-2009

Re: Pulse width of RESET in XADC module

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I made a test, with pulse width of 10ns, 100ns, 1us, 10us, 100us, 1ms, 100ms, 1s and 5s.

 

Only when the pulse width is 100us or upper, XADC can work correctly, the minimum width should be between 10us and 100us.

 

Chris

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Explorer
Explorer
3,092 Views
Registered: ‎09-02-2009

Re: Pulse width of RESET in XADC module

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I made a test, with pulse width of 10ns, 100ns, 1us, 10us, 100us, 1ms, 100ms, 1s and 5s.

 

Only when the pulse width is 100us or upper, XADC can work correctly, the minimum width should be between 10us and 100us.

 

Chris

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Xilinx Employee
Xilinx Employee
2,253 Views
Registered: ‎10-11-2007

Re: Pulse width of RESET in XADC module

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How do you determine that the reset actually occured? Keep in mind that the XADC will finish whatever the current sequence is before the reset takes hold.

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