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Adventurer
Adventurer
11,452 Views
Registered: ‎04-14-2016

QPLL not looking after line rate change

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Hello,

I want to change the line rate of a GTH transceiver from 10 to 8GBits during operation with DRP. In simulation all works fine, but one the FPGA the QPLL does lock after I trigger soft_reset (with starts the reset FSMs provided by the IP). Is this a hardware problem or a problem with by design. Without a change of the QPLL settings, the soft reset works fine on the FPGA.

I do the following changes: QPLL_FBDIV: 100->40, QPLL_REFCLOCK_DIV: 2->1, all others QPLL settings are on default values as generated by the IP wizard. I use vivado 2015.1. Reference clock in both cases is 200MHz. Any idea what I can do?

Additionally, I'm not sure that the GT transceiver took the data I write to, but I got the DRPRDY signal afterwards, can this be possible?

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1 Solution

Accepted Solutions
Adventurer
Adventurer
19,380 Views
Registered: ‎04-14-2016

Re: QPLL not looking after line rate change

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Hello,

I found the problem after debugging. A few bits are also changed (read-modify-write was not correct working in at least one DRP access operation in my design), but they ware not marked as an error in simulation and easy to overlook. But this was the problem and now the 8, 4 and 2GBits changes with DRP work correct.

Thank you for your help.

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14 Replies
Adventurer
Adventurer
11,446 Views
Registered: ‎04-14-2016

Re: QPLL not looking after line rate change

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At the moment, I set TX/RXPD to b01 and after reset to b00. This has not improved anything, but is it required to disable GTH before QPLL configuration change or not?
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Moderator
Moderator
11,399 Views
Registered: ‎02-16-2010

Re: QPLL not looking after line rate change

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The updates you mentioned look correct. Are you sure you are using GTH?

For GTX, there is a QPLL_CFG[6] attribute which selects QPLL
frequency band.
0: Upper band (9.8–12.5)
1: Lower band (5.93–8.0)

 

This attribute needs to be updated after QPLL attribute update for your use case.

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Adventurer
Adventurer
11,395 Views
Registered: ‎04-14-2016

Re: QPLL not looking after line rate change

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I am sure that I use GTH. The simulation is working as I already said, but not the design on the FPGA. I monitored it with an oscilloscope and after changing the QPLL settings the frequency measured increases (instead of decrease as a change from 10 to 8GBits should do). And after I trigger the soft_reset, the GTH stops any operation (no signal on oscilloscope). I also tested it for 10 to 4GBits, same result.

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Adventurer
Adventurer
11,372 Views
Registered: ‎04-14-2016

Re: QPLL not looking after line rate change

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I tried everything until now, but QPLL won't lock in after QPLL changes (in simulation it locks, on the FPGA not). But I think the FPGA is quite fine, because if I perform a reset (soft_reset) before QPLL changes, it locks. In post-implementation and post-synthese timing simulation, I found these warnings but I cannot understand what they mean (the files mentioned are part of the Xilinx IP):

launch_simulation: Time (s): cpu = 00:08:12 ; elapsed = 00:03:04 . Memory (MB): peak = 7468.789 ; gain = 1506.906 ; free physical = 6305 ; free virtual = 118659
run 35 us
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/FDRE.v" Line 299: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt0_rxresetfsm_i.wait_time_cnt_reg[1] at time 9088260 ps $width (R:9088155 ps, 9088260 ps, 400 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/FDRE.v" Line 299: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt0_rxresetfsm_i.wait_time_cnt_reg[4] at time 9088260 ps $width (R:9088155 ps, 9088260 ps, 400 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/FDRE.v" Line 299: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt0_txresetfsm_i.wait_time_cnt_reg[1] at time 13488190 ps $width (R:13488039 ps, 13488190 ps, 400 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/FDRE.v" Line 299: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt0_txresetfsm_i.wait_time_cnt_reg[4] at time 13488190 ps $width (R:13488039 ps, 13488190 ps, 400 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[13] at time 20052257 ps $width (G:20051994 ps, 20052257 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[4] at time 20052257 ps $width (G:20051994 ps, 20052257 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[5] at time 20052257 ps $width (G:20051994 ps, 20052257 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[9] at time 20052257 ps $width (G:20051994 ps, 20052257 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[1] at time 20052289 ps $width (G:20052026 ps, 20052289 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[6] at time 20052289 ps $width (G:20052026 ps, 20052289 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[7] at time 20052289 ps $width (G:20052026 ps, 20052289 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[10] at time 20052298 ps $width (G:20052035 ps, 20052298 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[11] at time 20052298 ps $width (G:20052035 ps, 20052298 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[12] at time 20052298 ps $width (G:20052035 ps, 20052298 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[14] at time 20052298 ps $width (G:20052035 ps, 20052298 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[15] at time 20052298 ps $width (G:20052035 ps, 20052298 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[2] at time 20052298 ps $width (G:20052035 ps, 20052298 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[0] at time 20052315 ps $width (G:20052052 ps, 20052315 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[3] at time 20052315 ps $width (G:20052052 ps, 20052315 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.address_ctrl_comp.DRP_DATA_OUT_reg[8] at time 20052315 ps $width (G:20052052 ps, 20052315 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.drpctrl_part_comp.drpCtrl_comp.wr_int_reg at time 20168301 ps $width (G:20168295 ps, 20168301 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20324305 ps $period (RXUSRCLK:20322305 ps, 20324305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20324305 ps $period (RXUSRCLK2:20322305 ps, 20324305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20324306 ps $period (TXUSRCLK:20322306 ps, 20324306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20324306 ps $period (TXUSRCLK2:20322306 ps, 20324306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20325303 ps $period (RXUSRCLK:20323303 ps, 20325303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20325303 ps $period (RXUSRCLK2:20323303 ps, 20325303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20325304 ps $period (TXUSRCLK:20323304 ps, 20325304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20325304 ps $period (TXUSRCLK2:20323304 ps, 20325304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20326305 ps $period (RXUSRCLK:20324305 ps, 20326305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20326305 ps $period (RXUSRCLK2:20324305 ps, 20326305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20326306 ps $period (TXUSRCLK:20324306 ps, 20326306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20326306 ps $period (TXUSRCLK2:20324306 ps, 20326306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20327303 ps $period (RXUSRCLK:20325303 ps, 20327303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20327303 ps $period (RXUSRCLK2:20325303 ps, 20327303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20327304 ps $period (TXUSRCLK:20325304 ps, 20327304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20327304 ps $period (TXUSRCLK2:20325304 ps, 20327304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20328305 ps $period (RXUSRCLK:20326305 ps, 20328305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20328305 ps $period (RXUSRCLK2:20326305 ps, 20328305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20328306 ps $period (TXUSRCLK:20326306 ps, 20328306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20328306 ps $period (TXUSRCLK2:20326306 ps, 20328306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20329303 ps $period (RXUSRCLK:20327303 ps, 20329303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20329303 ps $period (RXUSRCLK2:20327303 ps, 20329303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20329304 ps $period (TXUSRCLK:20327304 ps, 20329304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20329304 ps $period (TXUSRCLK2:20327304 ps, 20329304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20330305 ps $period (RXUSRCLK:20328305 ps, 20330305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20330305 ps $period (RXUSRCLK2:20328305 ps, 20330305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20330306 ps $period (TXUSRCLK:20328306 ps, 20330306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20330306 ps $period (TXUSRCLK2:20328306 ps, 20330306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20331303 ps $period (RXUSRCLK:20329303 ps, 20331303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20331303 ps $period (RXUSRCLK2:20329303 ps, 20331303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20331304 ps $period (TXUSRCLK:20329304 ps, 20331304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20331304 ps $period (TXUSRCLK2:20329304 ps, 20331304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20332305 ps $period (RXUSRCLK:20330305 ps, 20332305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20332305 ps $period (RXUSRCLK2:20330305 ps, 20332305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20332306 ps $period (TXUSRCLK:20330306 ps, 20332306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20332306 ps $period (TXUSRCLK2:20330306 ps, 20332306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20333303 ps $period (RXUSRCLK:20331303 ps, 20333303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20333303 ps $period (RXUSRCLK2:20331303 ps, 20333303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20333304 ps $period (TXUSRCLK:20331304 ps, 20333304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20333304 ps $period (TXUSRCLK2:20331304 ps, 20333304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20334305 ps $period (RXUSRCLK:20332305 ps, 20334305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20334305 ps $period (RXUSRCLK2:20332305 ps, 20334305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20334306 ps $period (TXUSRCLK:20332306 ps, 20334306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20334306 ps $period (TXUSRCLK2:20332306 ps, 20334306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20335303 ps $period (RXUSRCLK:20333303 ps, 20335303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20335303 ps $period (RXUSRCLK2:20333303 ps, 20335303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20335304 ps $period (TXUSRCLK:20333304 ps, 20335304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20335304 ps $period (TXUSRCLK2:20333304 ps, 20335304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20336305 ps $period (RXUSRCLK:20334305 ps, 20336305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20336305 ps $period (RXUSRCLK2:20334305 ps, 20336305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20336306 ps $period (TXUSRCLK:20334306 ps, 20336306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20336306 ps $period (TXUSRCLK2:20334306 ps, 20336306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20337303 ps $period (RXUSRCLK:20335303 ps, 20337303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20337303 ps $period (RXUSRCLK2:20335303 ps, 20337303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20337304 ps $period (TXUSRCLK:20335304 ps, 20337304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20337304 ps $period (TXUSRCLK2:20335304 ps, 20337304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20338305 ps $period (RXUSRCLK:20336305 ps, 20338305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20338305 ps $period (RXUSRCLK2:20336305 ps, 20338305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20338306 ps $period (TXUSRCLK:20336306 ps, 20338306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20338306 ps $period (TXUSRCLK2:20336306 ps, 20338306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20339303 ps $period (RXUSRCLK:20337303 ps, 20339303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20339303 ps $period (RXUSRCLK2:20337303 ps, 20339303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20339304 ps $period (TXUSRCLK:20337304 ps, 20339304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20339304 ps $period (TXUSRCLK2:20337304 ps, 20339304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20340305 ps $period (RXUSRCLK:20338305 ps, 20340305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20340305 ps $period (RXUSRCLK2:20338305 ps, 20340305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20340306 ps $period (TXUSRCLK:20338306 ps, 20340306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20340306 ps $period (TXUSRCLK2:20338306 ps, 20340306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20341303 ps $period (RXUSRCLK:20339303 ps, 20341303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20341303 ps $period (RXUSRCLK2:20339303 ps, 20341303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20341304 ps $period (TXUSRCLK:20339304 ps, 20341304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20341304 ps $period (TXUSRCLK2:20339304 ps, 20341304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20342305 ps $period (RXUSRCLK:20340305 ps, 20342305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20342305 ps $period (RXUSRCLK2:20340305 ps, 20342305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20342306 ps $period (TXUSRCLK:20340306 ps, 20342306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20342306 ps $period (TXUSRCLK2:20340306 ps, 20342306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20343303 ps $period (RXUSRCLK:20341303 ps, 20343303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20343303 ps $period (RXUSRCLK2:20341303 ps, 20343303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20343304 ps $period (TXUSRCLK:20341304 ps, 20343304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20343304 ps $period (TXUSRCLK2:20341304 ps, 20343304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20344305 ps $period (RXUSRCLK:20342305 ps, 20344305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20344305 ps $period (RXUSRCLK2:20342305 ps, 20344305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20344306 ps $period (TXUSRCLK:20342306 ps, 20344306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20344306 ps $period (TXUSRCLK2:20342306 ps, 20344306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20345303 ps $period (RXUSRCLK:20343303 ps, 20345303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20345303 ps $period (RXUSRCLK2:20343303 ps, 20345303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20345304 ps $period (TXUSRCLK:20343304 ps, 20345304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20345304 ps $period (TXUSRCLK2:20343304 ps, 20345304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20346305 ps $period (RXUSRCLK:20344305 ps, 20346305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20346305 ps $period (RXUSRCLK2:20344305 ps, 20346305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20346306 ps $period (TXUSRCLK:20344306 ps, 20346306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20346306 ps $period (TXUSRCLK2:20344306 ps, 20346306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20347303 ps $period (RXUSRCLK:20345303 ps, 20347303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20347303 ps $period (RXUSRCLK2:20345303 ps, 20347303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20347304 ps $period (TXUSRCLK:20345304 ps, 20347304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20347304 ps $period (TXUSRCLK2:20345304 ps, 20347304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20348305 ps $period (RXUSRCLK:20346305 ps, 20348305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20348305 ps $period (RXUSRCLK2:20346305 ps, 20348305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20348306 ps $period (TXUSRCLK:20346306 ps, 20348306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20348306 ps $period (TXUSRCLK2:20346306 ps, 20348306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20349303 ps $period (RXUSRCLK:20347303 ps, 20349303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20349303 ps $period (RXUSRCLK2:20347303 ps, 20349303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20349304 ps $period (TXUSRCLK:20347304 ps, 20349304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20349304 ps $period (TXUSRCLK2:20347304 ps, 20349304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20350305 ps $period (RXUSRCLK:20348305 ps, 20350305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20350305 ps $period (RXUSRCLK2:20348305 ps, 20350305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4347: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20350306 ps $period (TXUSRCLK:20348306 ps, 20350306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4349: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20350306 ps $period (TXUSRCLK2:20348306 ps, 20350306 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4335: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20351303 ps $period (RXUSRCLK:20349303 ps, 20351303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4337: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20351303 ps $period (RXUSRCLK2:20349303 ps, 20351303 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4346: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20351304 ps $period (TXUSRCLK:20349304 ps, 20351304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4348: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20351304 ps $period (TXUSRCLK2:20349304 ps, 20351304 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4336: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20352305 ps $period (RXUSRCLK:20350305 ps, 20352305 ps, 3053 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/GTHE2_CHANNEL.v" Line 4338: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.gt_comp.gt_unit_support_i.gt_unit_init_i.U0.gt_unit_i.gt0_gt_unit_i.gthe2_i at time 20352305 ps $period (RXUSRCLK2:20350305 ps, 20352305 ps, 3053 ps)
-- the rest, see attached file
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.drpctrl_part_comp.drpCtrl_comp.wr_int_reg at time 21048301 ps $width (G:21048295 ps, 21048301 ps, 350 ps)
WARNING - "/wrk/buildscratch/2015.1/continuous/20150427185245/data/verilog/src/unisims/LDCE.v" Line 170: Timing violation in scope gt_drp_unit_real_tb.GT_DRPUnit_TestSynth_GTx1_comp.drpctrl_comp.drpctrl_part_comp.drpCtrl_comp.wr_int_reg at time 21488301 ps $width (G:21488295 ps, 21488301 ps, 350 ps)
run: Time (s): cpu = 00:00:12 ; elapsed = 00:01:17 . Memory (MB): peak = 7477.465 ; gain = 0.371 ; free physical = 6197 ; free virtual = 118565
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Re: QPLL not looking after line rate change

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I'm using GTH (board has no GTZ connectors and I can only select between GTH and GTZ in IP wizard), but according to the transceiver guide (ug476), the output frequency is fclkpllin*N/(M*2), but if I calculated this with N=40, M=1 and fclkpllin=200MHz (reference clock) I get 200MHz*40/2=4GHz. Is that not too low anyway? Or is that not the QPLL frequency?

Additionally, I managed to get 8GBits with the board today, but I stored the bitstream file and tried it out some hours later again, this time the line rate was 8GBits from startup and before I active my switch process (10 to 8GBits switch). All tested with exaclty the same hardware and settings. Can it be, that the FPGA has any internal storage which is not erased during reconfiguration or what could be the problem?

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Re: QPLL not looking after line rate change

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I'm using GTH (board has no GTZ connectors and I can only select between GTH and GTZ in IP wizard), but according to the transceiver guide (ug476), the output frequency is fclkpllin*N/(M*2), but if I calculated this with N=40, M=1 and fclkpllin=200MHz (reference clock) I get 200MHz*40/2=4GHz. Is that not too low anyway? Or is that not the QPLL frequency?


 

Sorry, what I wrote was wrong I think. QPLL frequency is not the PLLClkout. So in my case of 8GBit/s, the QPLL frequency should also be 8GHz (as it is logically). But the other point remains unsolved, additionally when is change TXOUT_DIV, the GT transceivers stop operating at all, so I avoided to use TXOUT_DIV, but why? I found that TXOUT_DIV is something similar to TXRATE, which triggers a reset, maybe that is the problem but if I provide changes through DRP, will they be going into effect right away or after a full reset (in behaviour simulation, both works)?

 

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Re: QPLL not looking after line rate change

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I'm a bit confused now because in ug476 stands that PCI gen3 requires QPLL usage. PCI gen3 is 8GBits, but with CPLL max. 5,16GHz and TXOUT_DIV=1, this should be 5,16GHz*2/1=10,32GBits, so even exceeding PCI gen3. My question is now, are their any other limitations for the select of QPLL or CPLL in regard to the line rate. Because I have tried to switch from 10GBits to 4GBits with QPLL, which does not work on the FPGA while from 10GBits to 8GBits works fine. Please tell me in which line rate ranges QPLL and CPLL have to be selected because with the equations from ug476 PCI gen3 should be possible with CPLL. Do I see it right that QPLL only works until 1GBits and CPLL up to 10,32GBits?
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Re: QPLL not looking after line rate change

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In the steps mentioned above, I do not find TXSYSCLKSEL/RXSYSCLKSEL input to GT is changed. Are you doing this change?

When you change TXOUT_DIV/RXOUT_DIV, reset to GT is not asserted automatically. After changing GT attributes through DRP, you must assert reset to GT.
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Re: QPLL not looking after line rate change

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I change TXSYSCKLSEL only in case of switching between QPLL and CPLL. After changing the line rate and/or PLL switch I perform all full reset using the reset FSM of the Xilinx IP. Is this wrong? But just to make sure: 4Gbits is possible with both PLLs?

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Re: QPLL not looking after line rate change

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Here is wait I do (in according to ug476):

QPLL line rate change:

  1. Change QPLL_REFCLOCK_DIV to 1
  2. Change QPLL_FBDIV to 40 through DRP
  3. Change TXOUT_DIV and RXOUT_DIV to 2 through DRP
  4. Read QPLL_FBDIV to check if all ok
  5. Perform FULL reset using tx_reset_fsm manually, triggered by button on board

The result is, that after triggering reset the transceiver stops sending data (monitored with oscilloscope).

I didn't find the error, in all simulations it is working fine, but not one the FPGA, why?

Thank you!

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Re: QPLL not looking after line rate change

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I believe TXOUT_DIV and RXOUT_DIV should be 1 for 8Gbps operation.

Can you confirm the required QPLL settings by generating a GT wizard design at 8Gbps using QPLL?
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Re: QPLL not looking after line rate change

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You are quite right, I have forgotten to right that the change is from 10GBits to 4GBits. I have a working version of my design to change from 10GBits to 8GBits. I can also operate in the TXOUT_DIV=1 area through for example increasing the reference frequency. But I cannot switch into TXOUT_DIV=2, which is required to reach 4GBits. I have gain the values for 4, 6, 8, 10 and 13.1GBits already through generating example design for these line rates.

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Re: QPLL not looking after line rate change

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I have tested my design again, all simulations are fine but on the FPGA after providing the DRP changes, the QPLLLOCK vanishes and does not return after firing a full reset with the reset FSM. As I only use a TX, I set RXPD to 1b11 for power down, but there is not difference visible if I let the RX on. I have attatched my DCP file if this may contain any problems.

Switching to 13.1GBits does also not work (with 200->204.688MHz ref clk, QPLL_FBDIV=64, QPLL_REFCLOCK_DIV=1). Do I have to update any other values (I found not others in the 13.1GBits or 4GBits design examples which I would see as necessary)?

Thank you!

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Re: QPLL not looking after line rate change

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Hello,

I found the problem after debugging. A few bits are also changed (read-modify-write was not correct working in at least one DRP access operation in my design), but they ware not marked as an error in simulation and easy to overlook. But this was the problem and now the 8, 4 and 2GBits changes with DRP work correct.

Thank you for your help.

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