09-27-2018 01:09 AM
It is possible in a Spartan6 FPGA, once the Place & Route is completed, change slightly one of the IP core without forcing the restart of the complete process, changing the place & route?
The reason behind my question is because in our current design, we include several macros created with the Xilinx Core generator. One of this macros is a memory block which is pre-initialized with a content, which can change.
The FPGA itself has some parts that requires manual placement and dedicated STA to achieve the expected requirements, but every time I change the content of the memory block, ISE understand that there is a change in the sources and restart the complete process, changing the placement and routing, which requires new STA and manual analysis (very costly).
It is possible to do it but keeping the current design untouched?
09-27-2018 02:07 AM
In later device we have data2mem that can change the contents of the BRAMs in the design without changing the design. You can edit the contents in FPGA editor if you wish, or alternatively you can LOC down the BRAMs so when you re-run the flow after changing the contents the placement will be fixed.
Ill check on the data2mem to see if it supports Spartan-6, but its is only a small change, editing the contents in FPGA editor maybe easiest.
Then you just need to re-run BitGen
09-27-2018 02:14 AM
09-27-2018 03:34 AM
As far as I know, data2mem is not compatible with all type of memory blocks.
Our current memory block is created by combining different memory types and some of them are not compatible with data2mem.
I will recheck it again.
The current test I am doing is to extract place and route constraints for the complete design (200 MB file) and use it as input for the design. I expect that by Map and Place & Route ISE will use it and nothing will be changed compared to the previous versios. But this huge constraint file is loading since more than 4 hours. But it is still a possibility.
To change the content of the RAM directly in FPGA Editor looks something no so simple, but probably the best solution. I just have to check how is the format of this RAMs and which blocks we have.
In the core generator, I have to give only one file and this content is automatically distributed in the internal memory blocks in a transparent way.
Anyway, I will check all this possibilities.
Thank you for your support.
09-27-2018 04:11 AM
09-28-2018 04:02 AM
Honestly I didn't know about the existence of this option and it looks quite interesting.
Unfortunately, I have just activated this option, loading a previous NCD (without timing violations) and the results of the design implementation has been a disaster, with big timing violations.
Maybe I did something wrong? In the design, only minor changes has been introduced.
09-30-2018 03:45 PM
10-02-2018 01:23 AM
Ok. Yes. I change a couple a gates internally in one of the functions.
I didn't try it changing only the initialization of the memory. Ok, I will try.
It could also be a solutions.
10-03-2018 01:39 PM
10-04-2018 04:21 AM
I just have done the test:
1. Spartan 6 FPGA generated correctly.
2. I make "touch" on the ngc file used for the memory.
3 .ISE detects a change and request the restart of the implementation
4. I activate smartguide applying the previous NCD file.
5. Start the implementation
6 . Map fails with error Place 543: Design does not fit in the number of slices available in the device ...
What I am doing wrong? Actually I didn't change anything in the sources.