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9,832 Views
Registered: ‎01-21-2016

Reprogram FPGA usign internal signal (autoreset)

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Hello all,

I have a Nexys4 DDR and I want to reprogram it, as it's done with "PROG" button. My bitstream (.bin) is stored in QSPI.

Reprogram usign Vivado is not a solution because I'm doing a fault injection campaign and it is going to be reprogrammed several times.

As example I would like to connect the IPROG/Program_B signal to be triggered when something happens like the output of my circuit is "1", or using a switch.

How can I do that? Is there other solution? I've read documentation about multiboot but I don't want to load two bitstreams, only one and reprogram the FPGA with it when I want. I suppose that using the Program_b signal is the way to go but I don't know how I can use it.

Some code, tutorial or documentation would be appreciated.

Thank you

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1 Solution

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18,394 Views
Registered: ‎01-21-2016

Re: Reprogram FPGA usign internal signal (autoreset)

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Thank you all for your answer.

While I'm developing a way to reprogram the FPGA using Multiboot but with only one bitsteam as pointed here, I'm using a temporally solution I've seen in diligent forums.

 

For anyone in my situation, the solution is to take a wire, connect it to the PROG button on the FPGA and to a PMOD output. Inside Vivado, you have to connect the reprogram signal of your circuit (in my case SEM IP) to the PMOD pin like this

 

set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports reprogram_signal]; #IO_L20N_T3_A19_15 Sch=ja[1]

Be aware that the ouput must be inverted in order to work:

reprogram_signal <= NOT reprogram_signal_active

explanation.jpg

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4 Replies
Scholar drjohnsmith
Scholar
9,820 Views
Registered: ‎07-09-2009

Re: Reprogram FPGA usign internal signal (autoreset)

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partial re configuratoin could be what your looking for,

 

have a search 

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Xilinx Employee
Xilinx Employee
9,812 Views
Registered: ‎07-23-2012

Re: Reprogram FPGA usign internal signal (autoreset)

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As you are aware of multiboot concept, what you can do is instantiate ICAP in your design and you can specify the next boot address to the same address where your image lies. Once you assert IPROG through ICAP state machine code, you can initiate reboot and configure FPGA with the same image.
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Historian
Historian
9,796 Views
Registered: ‎01-23-2009

Re: Reprogram FPGA usign internal signal (autoreset)

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Take a look at this post - it seems to be asking the same question...

 

Avrum

18,395 Views
Registered: ‎01-21-2016

Re: Reprogram FPGA usign internal signal (autoreset)

Jump to solution

Thank you all for your answer.

While I'm developing a way to reprogram the FPGA using Multiboot but with only one bitsteam as pointed here, I'm using a temporally solution I've seen in diligent forums.

 

For anyone in my situation, the solution is to take a wire, connect it to the PROG button on the FPGA and to a PMOD output. Inside Vivado, you have to connect the reprogram signal of your circuit (in my case SEM IP) to the PMOD pin like this

 

set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports reprogram_signal]; #IO_L20N_T3_A19_15 Sch=ja[1]

Be aware that the ouput must be inverted in order to work:

reprogram_signal <= NOT reprogram_signal_active

explanation.jpg

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