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Visitor val_r
Visitor
484 Views
Registered: ‎09-09-2018

SDIF-3 Audio Interface - help a newbie

Hi folks!

 

I'm a newbie, very new to the exciting FPGA-VHDL design world, trying to design an encoder for the SDIF-3 audio coding (a sort of Manchester coding scheme), -code attached-

Signal generated from an external audio ADC board must get encoded by this design.

 

Simulation actually works just fine.

I'm actually using a Basys3/Artix 7 to experiment, then I'm planning to migrate to a CPLD.

 

From the official Sony's document, this is what the SDIF3 encoding does:

 

sdif3v10-2.png

 

Since the A/D conversion chip already works with an external MCLK, I thought to use it to generate an internally divided

i_clk which is a double-data bit rate, i.e. the 'Clock' signal in the above picture. 

 

Unfortunately, because of skew (I think), encoding is prone to error.

The following is a scope snap of "data_l" input (ch1, yellow), and the encoded output "out_l" (ch2, blue):

 

TEK0009.JPG

not quite correct! :(

 

I did measure the dsd bitclock generated from the ADC board, and the "i_clk" divided DDR clock, which governs the process,

I've measured around 21ns of skew.

The following snap shows i_clk(ch1), and dsdclk (ch2, blue):

 

TEK0006.JPG

 

Can this be the cause of uncorrect encoding?

What would be the best way to correct this? Re-sync dsd-data to i_clk? how?

Please see my code attached below.

 

Any hint/help greatly appreciated!

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Visitor val_r
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427 Views
Registered: ‎09-09-2018

Re: SDIF-3 Audio Interface - help a newbie

Okay, changed little things in my new code (attached):

initialized  y_reg signal to '0', assigned DFF outputs to out_l and out_r instead of passing through intermediate signals.

 

Now it seems to work smoothly for the DSD 1x stream, (2.8224MHz original data, 5.6448MHz internal clock i_clk ).

In this configuration the external 22.5792MHz clock is divided by 4 to get the 5.6448MHz internal clock.

 

In the DSD 2x configuration, where the original data stream is doubled, at 5.6448Mbps, and i_clk is 11.2896MHz, being divided by 2 from the external Master clock, 

I encounter a sync problem, the internal divided clock, i_clk , switches a little before the datastream transitions, causing incorrect coding.

 

The following is the scope snap of incorrect 5.6Mbps encoding, Ch1 (yellow) is the original input data stream,

Ch 2 (blue) is the encoded stream:

 

13_data_r-out_r_5.6.jpg

 

 

and the snap of datastream (yellow), against out-of-sync i_clk (blue):

14_data_l-i_clk_11.2896MHz.jpg

 

clock is leading data.

 

Correct encoding should look like the following snap (at 2.8224Mbps):

10_data_l-out_l_2.8224MHz.jpg

 

How can I correct this?

Any hint?

 

Thank you in advance!

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Visitor val_r
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Registered: ‎09-09-2018

Re: SDIF-3 Audio Interface - help a newbie

Anyone?
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