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Contributor
Contributor
231 Views
Registered: ‎03-02-2015

SGMII 1G/2.5G - Artix 7

Currently using an SGMII wrapper around the transceivers on artix for getting gigabit (1G) Ethernet. For next gen design there is talk of using  2.5G. 

Can a single FPGA bitfile support 1G and 2.5G on the same pins? So in a legacy backplane it would be configured for 1G, in a new backplane it will be configured for 2.5G? 

This would have to be as controlled, or possible (rather not) done through partial reconfig.

What are the options here?

Thank you!

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Adventurer
Adventurer
212 Views
Registered: ‎01-28-2013

Re: SGMII 1G/2.5G - Artix 7

A 2.5G PHY usually support multiple speeds including 1G. So you should be able support both using 2.5G core. 

It should be just the logic core update on the FPGA side. Hardware changes are a totally different thing.

This is just a generic point. It's better to think it through considering the PHY, Host interfaces, Copper/ Optical support, Device specific Transceiver.

 

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