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Observer himanshu28
Observer
1,209 Views
Registered: ‎05-17-2018

Sampling rate of XADC

The conversion rate of XADC in 7-series FPGAs is 1 MSPS maximum. But I am working on filter designing which requires the ADC sampling rate to be 1 KSPS. . The minimum possible conversion rate is 39 KSPS.

 

Please giude me how to get a sampling rate of 1 KSPS in XADC. I am using Zybo board and its built-in XADC in DRP mode.

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6 Replies
Moderator
Moderator
1,200 Views
Registered: ‎04-18-2011

Re: Sampling rate of XADC

hi @himanshu28

 

On the other thread you had I've already said that if you want to you can use the XADC in event mode and apply a Convert Start at this 1Khz rate. 

 

Alternatively, you could set up the XADC to convert at 64Ksps or 256Ksps in sequencer mode and apply averaging to the result. 

averaging can be x64 or x256 this means you will now get a new result every 1ms. 

 

Keith 

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1,179 Views
Registered: ‎01-22-2015

Re: Sampling rate of XADC

-or, you could setup the XADC for 1 MSPS rate and only use every 1000th sample - giving effective sample rate of 1KSPS.

 

Mark

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Scholar jmcclusk
Scholar
1,172 Views
Registered: ‎02-24-2014

Re: Sampling rate of XADC

That's probably a bad idea to do subsampling for 2 reasons..   poor Signal to Noise ratio, and it also opens the door to aliasing from frequencies over 500 Hz.  

 

It's a really good idea to do sample averaging with the 1M sample rate down to 1 KHz.

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1,149 Views
Registered: ‎01-22-2015

Re: Sampling rate of XADC

If the XADC sampling rate is high (eg. 1MSPS) then averaging the counts data produced by the XADC can reduce signal aliasing into the 500Hz signal band of @himanshu28.  However, it is far better to place an analog lowpass filter ahead of the digitizer to reduce aliasing.  Since @himanshu28 wants to sample at 1KSPS, perhaps his signal is already bandlimited to 500Hz? 

 

In general, I find that the inherent SNR of a digitizer does not change much over the sampling frequencies we are discussing.  However, the XADC is a noisy digitizer with 16-bit output but only 12-bits effective (the 4 LSBs corrupted by noise).  So, I agree that averaging the counts data can improve SNR and resolution of the XADC (see also ug480, pg25).

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Observer himanshu28
Observer
1,132 Views
Registered: ‎05-17-2018

Re: Sampling rate of XADC

How can I take the output for every 1000th samples? Please guide me through this.

Thanks .
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1,119 Views
Registered: ‎01-22-2015

Re: Sampling rate of XADC

@himanshu28

 

  • Learn about the Xilinx IP called the XADC Wizard. Xilinx document ug480 is where you learn about this IP. I see that Keith has already recommended this document to you.

  • Use the XADC Wizard to configure the XADC digitizer. I see from your other post that you have started doing this and that you plan to communicate with the XADC using the DRP interface.

  • Write software to communicate with the XADC.  I see that Keith has already given you guidance in your other post for writing this software. You might also look at the zip-file called ug480_7Series_XADC.zip that comes with ug480 document. This zip file contains HDL software that you can use to communicate with the XADC via the DRP interface.

  • Use your software to trigger the XADC to do a conversion every 1ms. -and to read the results of the conversion (counts data) from the XADC via the DRP interface.

  • Use your software to send the counts data to the digital filter you are designing.