06-07-2018 03:41 AM
The conversion rate of XADC in 7-series FPGAs is 1 MSPS maximum. But I am working on filter designing which requires the ADC sampling rate to be 1 KSPS. . The minimum possible conversion rate is 39 KSPS.
Please giude me how to get a sampling rate of 1 KSPS in XADC. I am using Zybo board and its built-in XADC in DRP mode.
06-07-2018 03:52 AM
On the other thread you had I've already said that if you want to you can use the XADC in event mode and apply a Convert Start at this 1Khz rate.
Alternatively, you could set up the XADC to convert at 64Ksps or 256Ksps in sequencer mode and apply averaging to the result.
averaging can be x64 or x256 this means you will now get a new result every 1ms.
06-07-2018 04:53 AM
-or, you could setup the XADC for 1 MSPS rate and only use every 1000th sample - giving effective sample rate of 1KSPS.
06-07-2018 05:48 AM
That's probably a bad idea to do subsampling for 2 reasons.. poor Signal to Noise ratio, and it also opens the door to aliasing from frequencies over 500 Hz.
It's a really good idea to do sample averaging with the 1M sample rate down to 1 KHz.
06-07-2018 09:10 AM - edited 06-07-2018 09:26 AM
If the XADC sampling rate is high (eg. 1MSPS) then averaging the counts data produced by the XADC can reduce signal aliasing into the 500Hz signal band of @himanshu28. However, it is far better to place an analog lowpass filter ahead of the digitizer to reduce aliasing. Since @himanshu28 wants to sample at 1KSPS, perhaps his signal is already bandlimited to 500Hz?
In general, I find that the inherent SNR of a digitizer does not change much over the sampling frequencies we are discussing. However, the XADC is a noisy digitizer with 16-bit output but only 12-bits effective (the 4 LSBs corrupted by noise). So, I agree that averaging the counts data can improve SNR and resolution of the XADC (see also ug480, pg25).
06-07-2018 05:57 PM - edited 06-07-2018 05:58 PM