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Explorer
Explorer
2,118 Views
Registered: ‎10-29-2008

SelectIO ISERDES as high-speed shift-register

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In reviewing the "Advanced SelectIO Logic Resources" it seems like the SERDESE2 can be considered/used-as a high-speed shift-register.  Serial data clocked/shifted in and accessed inside the FPGA as parallel.  Thus, if my design calls for an 8-bit shift register I can use the internal ISERDES instead of including an external shift-register on the board.

 

Is this a correct understanding?

 

Can data be clocked into it a 1GHz?  Would this require operating in double data rate (DDR) mode?

 

The 7-Series Overview documentation says:

"Each I/O pin possesses an 8-bit IOSERDES (ISERDES and
OSERDES) capable of performing serial-to-parallel or parallel-to-serial conversions with programmable widths of 2, 3, 4, 5,
6, 7, or 8 bits"

This would appear to indicate a very large quantity of  ISERDES  are available (on the order of the pin count). 

Is there a limit on how many of them can be run at a high-input clock rate (e.g. 1GHz)?

 

 

 

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Moderator
Moderator
2,794 Views
Registered: ‎04-18-2011

Re: SelectIO ISERDES as high-speed shift-register

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@digitalone

 

There is a section in the IO User Guide UG471 that deals with the clocking scheme for the ISERDES. 

 

Clocking the ISERDES in Spartan-6 is a more nuanced affair. 

Take a look here:

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

 

To get higher data rates you would need to be coming in directly with the bit clock and you would need to be using the BUFIO. Take a look af figure 1-15 on page 15. 

Also special care has to be taken with BUFIO because they do not span the full bank in S6. 

Please see UG382 to understand the clock structure of the IO bank in the s6 device 

 

 

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7 Replies
Moderator
Moderator
2,078 Views
Registered: ‎04-18-2011

Re: SelectIO ISERDES as high-speed shift-register

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Hi @digitalone

 

The IO Logic ISERDES is meant to be used for receiving high speed source synchronous data. 

 

I don't know what the objective here is. You are talking about using it so that you don't need a shift register on the board. 

 

In principle it can capture data at 1Gbps. 

This data rate is mostly associated with differential signalling.

In practice there is almost always a need to have some known clock and data alignment, then you need there is a need for the bit clock to be deskewed so that the sampling point is at the most stable point of the data eye. 

There is usually a need to have some sort of frame signal or training pattern so that the 8 bit word alignment is good. read about the bitslip logic in this case. 

 

It would be better if you showed us what your circuit looks like with some sort of block diagram... 

 

 

It would be interne

 

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Explorer
Explorer
2,055 Views
Registered: ‎10-29-2008

Re: SelectIO ISERDES as high-speed shift-register

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Yes, I understand the I/O SERDES are meant for source synchronous data and the need for clock/data alignment, stable sampling-point, deskew etc. For this application I don't need the reads to line up perfectly on 8-bit boundaries.  I just need to read data in, in  parallel so the FPGA logic doesn't have to run at the 1Gbps speeds, only div-by-8 = 125MHz.  If the FPGA logic could be clocked at 1GHz I could just implement the shift-registers in the logic.

 

I can't share a circuit diagram.  Basically there are many input shift-registers all clocked at 1GHz with LVDS data being shifted in.   Instead of having to have all the high-speed shift-register chips on the board interfacing externally to the FPGA via parallel read, I would like to use the ISERDES as the shift-register so the serial-to-parallel happens inside the FPGA.

 

Is there any reason (baring concerns mentioned at the top) that an ISERDES cannot be used as a high-speed input shift-register?

 

 

 

 

 

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Moderator
Moderator
2,050 Views
Registered: ‎04-18-2011

Re: SelectIO ISERDES as high-speed shift-register

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I suppose as long as you have a way to ensure you capture the data when it is stable then it should work in the way you say. 

The number of ISERDES available is equal to the number of the LVDS pairs basically. 

 

 

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Explorer
Explorer
2,046 Views
Registered: ‎10-29-2008

Re: SelectIO ISERDES as high-speed shift-register

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As far as clocking to support the 1Gbps input rate.

 

Is there a difference on which FPGA devices can support this rate based on if I use an external clock vs. an internal clock?

 

It looks like an MMCM is required if using an internal clock source. 

Looking at DC switching characteristics of the MMCM it would seem only Virtex-7 and Kintex-7 support this rate.

But then looking at the BUFG, BUFIO, etc. I noticed they max out at around 800MHz so it would appear the MMCM output cannot be buffered at this rate.

 

Can other lower performance devices (Artix-7 and Spartan-7) support this rate if the clock is provided externally?

 

Is there any possibly of supporting this input data rate with a Spartan-6 (external or internal clock)?

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Moderator
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2,030 Views
Registered: ‎04-18-2011

Re: SelectIO ISERDES as high-speed shift-register

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You can't say in one post:

 

Yes, I understand the I/O SERDES are meant for source synchronous data and the need for clock/data alignment, stable sampling-point, deskew etc.

 

Then in the next post say:

 

Is there a difference on which FPGA devices can support this rate based on if I use an external clock vs. an internal clock?

It looks like an MMCM is required if using an internal clock source. 

Looking at DC switching characteristics and the MMCM it would seem only Virtex-7 and Kintex-7 support this rate.

 

There has to be a phase relationship of some sort between the data and the clock that is going to capture it particularly at higher data rates. 

Now you are talking about using an internal clock from an MMCM to clock the ISERDES. 

what has the input clock of this MMCM got to do with the data? is it 1GHZ/8?? Is the MMCM going to multiply the 125Mhz clock up to give the bit clock and a deskewed version of itself to drive the parallel clock of the ISERDES?

 

You need a 500Mhz clock to capture this. 

BUFG can do this operate at this frequency. 

The ISERDES would need to run in DDR mode, you would still be better off clearly defining the clock and data arrangement here. 

How can you be sure you meet the input set up and hold time on the ISERDES?

 

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Explorer
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Registered: ‎10-29-2008

Re: SelectIO ISERDES as high-speed shift-register

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Thank you for your response.

 

Yes, I know there has to be phase relationships between clock and data as well as setup/hold considerations.  I would have to deal with the same issues with external shift-registers and their clock and data relationships etc.  This is something we are definitely going to have to deal with.

 

What I am trying to determine now are clocking possibilities and which Xilinx 7-series (or Spartan-6) devices can support the ISERDES at 1Gbps.

 

Because you mentioned running ISERDES in DDR that makes sense that BUFG only has to run at 500Mhz. 

It looks like even the Spartan-7 can support that in the (-2) speed grade.

The Spartan-6 is a little more confusing. It has BUFGMUX max at 400MHz, but then has 1080Mhz (-3) DDR LVDS ISERDES.

 

In general, which 7-series devices are the best choice for running at 1Gbps?  Is Spartan-6 even an option?

 

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Moderator
Moderator
2,795 Views
Registered: ‎04-18-2011

Re: SelectIO ISERDES as high-speed shift-register

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@digitalone

 

There is a section in the IO User Guide UG471 that deals with the clocking scheme for the ISERDES. 

 

Clocking the ISERDES in Spartan-6 is a more nuanced affair. 

Take a look here:

http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

 

To get higher data rates you would need to be coming in directly with the bit clock and you would need to be using the BUFIO. Take a look af figure 1-15 on page 15. 

Also special care has to be taken with BUFIO because they do not span the full bank in S6. 

Please see UG382 to understand the clock structure of the IO bank in the s6 device 

 

 

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