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Visitor f1t3
Visitor
463 Views
Registered: ‎09-06-2018

SelectIO Interface Wizard reset procedure / reset delay

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Hello, 

 

PG070 states in Table 2-1 for the io_reset signal: 

 

I/O reset: Reset connected to all other elements in the circuit. For proper functionality, io_reset has to be deasserted when the clocks
to SERDES are stable. Due to this requirement, io_reset must be deasserted after some cycles of clk_reset deassertion. For 8:1 serialization, sixteen cycles delay of I/O clock between clk_reset and io_reset can be used.

 

What is the most common/convenient way to achieve this 16 clock cycles delay? Attached is my current design, in which the data_out_to_pins stay dead. I suspect this is beacause of the wrong reset procedure, or am I totally wrong here? 

reset.png
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Visitor f1t3
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Registered: ‎09-06-2018

Re: SelectIO Interface Wizard reset procedure / reset delay

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Never mind, a simple RAM-based shift register does the job.

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Visitor f1t3
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406 Views
Registered: ‎09-06-2018

Re: SelectIO Interface Wizard reset procedure / reset delay

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Never mind, a simple RAM-based shift register does the job.

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