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Visitor rahuljha08
Visitor
140 Views
Registered: ‎06-18-2019

Signal Integrity

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I am using Artix 7 (2.5V) IBIS model for signal integrity simulation. For FPGA as driver which model name(e.g. LVTTL or SSTL) used as SPI Clock ?

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Xilinx Employee
Xilinx Employee
96 Views
Registered: ‎06-06-2018

Re: Signal Integrity

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HI @rahuljha08 

since CCLK is in bank0. All active dedicated output pins operate at the VCCO_0 voltage level with the output standard set to LVCMOS, 12 mA drive, fast slew rate.

If you download IBIS Models from Xilinx website it will generic. So please open Implimented Design and generate IBIS Model, then IBIS Model will be mapped to the CCLK Pin based on the IO Standard you have set. For more to generate IBIS Models refer https://www.xilinx.com/support/answers/50957.html.

For your case you need LVCMOS12 Model.

Hope this helps.

Regards,

Deepak D N

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Xilinx Employee
Xilinx Employee
97 Views
Registered: ‎06-06-2018

Re: Signal Integrity

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HI @rahuljha08 

since CCLK is in bank0. All active dedicated output pins operate at the VCCO_0 voltage level with the output standard set to LVCMOS, 12 mA drive, fast slew rate.

If you download IBIS Models from Xilinx website it will generic. So please open Implimented Design and generate IBIS Model, then IBIS Model will be mapped to the CCLK Pin based on the IO Standard you have set. For more to generate IBIS Models refer https://www.xilinx.com/support/answers/50957.html.

For your case you need LVCMOS12 Model.

Hope this helps.

Regards,

Deepak D N

--------------------------------------------------------------------------------------------

Please reply or give kudo or Accept as a Solution.

--------------------------------------------------------------------------------------------

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Visitor rahuljha08
Visitor
64 Views
Registered: ‎06-18-2019

Re: Signal Integrity

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Hi @ddn,

Thanks for reply.  

Which logic I have to follow for configuration pins in Artix 7?

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