01-05-2016 01:31 PM
The waveforms shown in Figure 13 of xapp894 show the simulation results of the high-speed receiver interface depicted in Figure 11. However, the received common mode voltage shown by the upper waveform of Figure 13 is about 200mV which is substantially less than the 300mV minimum LVDS_25 Vicm required by the Spartan-6 and 7-Series datasheets. Can someone explain this apparent inconsistency?
01-05-2016 02:01 PM
The common mode voltage must be high enough so that the peak to peak voltages do not go below ground, and do not go above Vcco. The differential receiver circuit is full CMOS, so it operates rail to rail just fine.
Yes, staying with the recommended (standard) values is good, but often it is not required at all (things still work just fine).
XAPP are built and tested, working examples. If you wish to make a product from one, it is up to you to set the specifications and requirements, and see to it they are met.
01-05-2016 02:17 PM
Austin, thanks for the reply. Your explanation seems fine for a demo system, but for a production-volume system, how can a designer be sure that a Xilinx Spartan-6 or 7-Series fpga can reliably receive SLVS-200 when the datasheet does not seem to support it? This can be a hard hurdle to overcome in design reviews. Are you recommending that designers rely on simulation and ignore the datasheet?
01-05-2016 02:23 PM
I would never say to ignore the datasheet!
I am only explaining how the device is designed.
Some customers take advantage of this knowledge most do not.
Is it a risk? Almost surely not (we are not going to redesign the comparator).
But, explaining that to a no-nonsense project manager is a no-go, I would agree.