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Visitor bhunt
Visitor
114 Views
Registered: ‎10-08-2008

Spartan-7 LVCMOS33 I/O list displaying in red

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Hi there,

Using Vivado 2019.1, on an S7 design with 3.3V I/O. When I'm viewing the implemented design's IO Ports tab, the I/O Std LVCMOS33* is displayed in red text. It makes me nervous, but I don't have any DRC warnings or other messages indicating there's a problem. Is this normal?

image.png

I have these settings in my constraints:

set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Thanks,

BryanH

 

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Moderator
Moderator
68 Views
Registered: ‎11-09-2015

Re: Spartan-7 LVCMOS33 I/O list displaying in red

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Hi @bhunt 

You need to make sure all the pins in the same IO bank are using the compatible I/O standards.Refer to UG471 page97:

selectIO.JPG

And also you need to make sure the pins you are trying to select are on a HR I/Os bank. From DS189 under table 8:

spartan.JPG

You can check if a pin is in an HR (High Range) bank by placing your pointer over it:

IOs.JPG

With that said, it can be red and perfectly fine. If you can generate a bitstream, that means this is fine. If there is error preventing the bitstream generation, you can go back to what I mentioned

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
69 Views
Registered: ‎11-09-2015

Re: Spartan-7 LVCMOS33 I/O list displaying in red

Jump to solution

Hi @bhunt 

You need to make sure all the pins in the same IO bank are using the compatible I/O standards.Refer to UG471 page97:

selectIO.JPG

And also you need to make sure the pins you are trying to select are on a HR I/Os bank. From DS189 under table 8:

spartan.JPG

You can check if a pin is in an HR (High Range) bank by placing your pointer over it:

IOs.JPG

With that said, it can be red and perfectly fine. If you can generate a bitstream, that means this is fine. If there is error preventing the bitstream generation, you can go back to what I mentioned

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Tags (1)
0 Kudos