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Visitor lalit
Visitor
1,400 Views
Registered: ‎07-01-2018

Virtex-5 space grade unused IOs and decoupling caps

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Hi,

We are planning to use Virtex-5 space grade FPGA for a space project. But before this, we will develop a prototype with Virtex-5 XC5VFX130T.

PCB layout will be designed keeping in mind the Virtex-5 space grade pin out so that we don't need to design the PCB layout again.

Now , we have many unused IO pins.

 My questions are for both space grade and non space grade Virtex-5 FPGA:

  1. Can I connect unused IO to ground of both space grade and non space grade version and in doing so do I need to take care of logic level of HSWAPEN pin?
  2. What to do with VCCO of unused IO banks? Do I need to connect them to suitable voltage?
  3. It is mentioned that Virtex-5 XC5VFX130T have built-in decoupling caps. Do I need to connect additional decoupling caps for both space grade and non space grade version.?

Thanks & Regards

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Community Manager
Community Manager
1,068 Views
Registered: ‎07-23-2015

Re: Virtex-5 space grade unused IOs and decoupling caps

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@lalit 


As per "UG203" we are not using any external decoupling capacitors for VCCO of any bank.

Is this OK with FPGA? Will our design work without external decoupling capacitors?

 


Any reason to not have decoupling caps? 

I would recommend you go through the Basic PDS principles from Page#22 of UG203 to understand the role of decoupling caps. 

 

There are on-package decaps for some packages but those come into effect only at high frequency. For the lower frequency range, you will need on-board decaps. It is always safe to have on-board decoupling caps and the quantity can vary from UG203. However that quantity will need to come from your PDN simulations. 

 

Since you plan to use a Space Grade part in future on this board, I would recommend you touch base with your FAE to make sure you are designing it right. We can't answer Space Grade specific queries on forums. This query being common for both commercial/space grade was answered. 

- Giri
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Visitor lalit
Visitor
1,322 Views
Registered: ‎07-01-2018

Re: Virtex-5 space grade unused IOs and decoupling caps

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Hello All,

Please reply to this question.Any help would be highly appreciated.

 

Kind Regards,

Lalit

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Community Manager
Community Manager
1,302 Views
Registered: ‎07-23-2015

Re: Virtex-5 space grade unused IOs and decoupling caps

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@lalit 

  1. Yes, it is recommended to connect unused IO Pins to GND if using the device in high altitude environments. HSWAPEN will only enable a weak-pull's during configuration and your setting of unused pins in bitstream should match to what you doing to the unused IO pins. In bitstream leave unused pins as float option since you are externally tying them to GND. 
  2. Connect them to a plane either GND or a power plane. 
  3. Check UG203

Also refer to UG520 Chapter 8 that describes the Pin Cross-Reference Space Grade device with a Commercial Part

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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Visitor lalit
Visitor
1,081 Views
Registered: ‎07-01-2018

Re: Virtex-5 space grade unused IOs and decoupling caps

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Hi Gnarahar,

Thanks for the reply.

Right now we are using XC5VFX130T-1FFG1738I virte-5 FPGA as Image Processor for interfacing it with Image Sensor. DDR2, NOR,SRAM are also connected to FPGA.

As per "UG203" we are not using any external decoupling capacitors for VCCO of any bank.

Is this OK with FPGA? Will our design work without external decoupling capacitors?

Please share your views.

It will be of great help if other Users of this forum, who have faced any issue because of decoupling capacitors ,can also share their views.

Thanks

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Community Manager
Community Manager
1,069 Views
Registered: ‎07-23-2015

Re: Virtex-5 space grade unused IOs and decoupling caps

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@lalit 


As per "UG203" we are not using any external decoupling capacitors for VCCO of any bank.

Is this OK with FPGA? Will our design work without external decoupling capacitors?

 


Any reason to not have decoupling caps? 

I would recommend you go through the Basic PDS principles from Page#22 of UG203 to understand the role of decoupling caps. 

 

There are on-package decaps for some packages but those come into effect only at high frequency. For the lower frequency range, you will need on-board decaps. It is always safe to have on-board decoupling caps and the quantity can vary from UG203. However that quantity will need to come from your PDN simulations. 

 

Since you plan to use a Space Grade part in future on this board, I would recommend you touch base with your FAE to make sure you are designing it right. We can't answer Space Grade specific queries on forums. This query being common for both commercial/space grade was answered. 

- Giri
--------------------------------------------------------------------------------------------------------------------
There's no such thing as a stupid question. Feel free to ask but do a quick search to make sure it ain't already answered.
Keep conversing, give Kudos and Accept Solution when you get one.
-----------------------------------------------------------------------------------------------------------------------
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Visitor lalit
Visitor
1,042 Views
Registered: ‎07-01-2018

Re: Virtex-5 space grade unused IOs and decoupling caps

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Hi Gnarahar,

Thanks for the suggestions.

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