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Observer bujosa
Observer
4,975 Views
Registered: ‎05-24-2011

Virtex 7 pcie pinout

xc7vx485tffg1157-2

ise 13.2

 

How do I translate what gets created in pcie core ucf to an actual pin number?

This is what is in the ucf:

IBUFDS_GTE2_X1Y5

GTXE2_CHANNEL_X1Y11

PCIE_X1Y0

 

I looked in UG475 FPGA Packaging and Pinout and UG476 GTX Transceivers.

 

I had the same problem in virtex 6 and had to do a build to figure out what the pinout was.  Unfortunately virtex 7 pcie coregen is broken and can not build the core (see my other post).

 

 

 

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Xilinx Employee
Xilinx Employee
4,690 Views
Registered: ‎03-18-2008

Re: Virtex 7 pcie pinout

The best place to extract this information would be to look at the fabric in FPGA Editor. You can open up a new design in FPGA Editor, find the GTX at location x1Y11 and trace it back to the pins.
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Xilinx Employee
Xilinx Employee
4,611 Views
Registered: ‎08-07-2007

Re: Virtex 7 pcie pinout

hi,

 

for GTX_channel LOC, when you look at ug476, did you see the section 'FFG1157 Package Placement Diagram'?

 

boris

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